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Commit 7b93eccf authored by Timur Tabi's avatar Timur Tabi Committed by Kumar Gala
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powerpc/85xx: clamp the P1022DS DIU pixel clock to allowed values 



To ensure that the DIU pixel clock will not be set to an invalid value,
clamp the PXCLK divider to the allowed range (2-255).  This also acts as
a limiter for the pixel clock.

Signed-off-by: default avatarTimur Tabi <timur@freescale.com>
Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
parent ebf714ff

arch/powerpc/platforms/85xx/p1022_ds.c

+6 −1
Original line number Diff line number Diff line
@@ -195,8 +195,13 @@ void p1022ds_set_pixel_clock(unsigned int pixclock) 
	do_div(temp, pixclock);

	freq = temp;



	/* pixclk is the ratio of the platform clock to the pixel clock */

	/*

	 * 'pxclk' is the ratio of the platform clock to the pixel clock.

	 * This number is programmed into the CLKDVDR register, and the valid

	 * range of values is 2-255.

	 */

	pxclk = DIV_ROUND_CLOSEST(fsl_get_sys_freq(), freq);

	pxclk = clamp_t(u32, pxclk, 2, 255);



	/* Disable the pixel clock, and set it to non-inverted and no delay */

	clrbits32(&guts->clkdvdr,