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Commit 7b933421 authored by Florian Fainelli's avatar Florian Fainelli Committed by Ralf Baechle
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MIPS: BCM63XX: add support for BCM3368 Cable Modem 



The Broadcom BCM3368 Cable Modem SoC is extremely similar to the
existing BCM63xx DSL SoCs, in particular BCM6358, therefore little effort
in the existing code base is required to get it supported. This patch adds
support for the following on-chip peripherals:

- two UARTS
- GPIO
- Ethernet
- SPI
- PCI
- NOR Flash

The most noticeable difference with 3368 is that it has its peripheral
register at 0xfff8_0000 we check that separately in ioremap.h. Since
3368 is identical to 6358 for its clock and reset bits, we use them
verbatim.

Signed-off-by: default avatarFlorian Fainelli <florian@openwrt.org>
Cc: linux-mips@linux-mips.org
Cc: cernekee@gmail.com
Cc: jogo@openwrt.org
Patchwork: https://patchwork.linux-mips.org/patch/5499/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent ae8de61c

arch/mips/bcm63xx/Kconfig

+4 −0
Original line number Diff line number Diff line 
menu "CPU support"

	depends on BCM63XX



config BCM63XX_CPU_3368

	bool "support 3368 CPU"

	select HW_HAS_PCI



config BCM63XX_CPU_6328

	bool "support 6328 CPU"

	select HW_HAS_PCI

arch/mips/bcm63xx/clk.c

+9 −9
Original line number Diff line number Diff line
@@ -84,7 +84,7 @@ static void enetx_set(struct clk *clk, int enable) 
	else

		clk_disable_unlocked(&clk_enet_misc);



	if (BCMCPU_IS_6358()) {

	if (BCMCPU_IS_3368() || BCMCPU_IS_6358()) {

		u32 mask;



		if (clk->id == 0)
@@ -110,8 +110,7 @@ static struct clk clk_enet1 = { 
 */

static void ephy_set(struct clk *clk, int enable)

{

	if (!BCMCPU_IS_6358())

		return;

	if (BCMCPU_IS_3368() || BCMCPU_IS_6358())

		bcm_hwclock_set(CKCTL_6358_EPHY_EN, enable);

}
@@ -155,8 +154,9 @@ static struct clk clk_enetsw = { 
 */

static void pcm_set(struct clk *clk, int enable)

{

	if (!BCMCPU_IS_6358())

		return;

	if (BCMCPU_IS_3368())

		bcm_hwclock_set(CKCTL_3368_PCM_EN, enable);

	if (BCMCPU_IS_6358())

		bcm_hwclock_set(CKCTL_6358_PCM_EN, enable);

}
@@ -211,7 +211,7 @@ static void spi_set(struct clk *clk, int enable) 
		mask = CKCTL_6338_SPI_EN;

	else if (BCMCPU_IS_6348())

		mask = CKCTL_6348_SPI_EN;

	else if (BCMCPU_IS_6358())

	else if (BCMCPU_IS_3368() || BCMCPU_IS_6358())

		mask = CKCTL_6358_SPI_EN;

	else if (BCMCPU_IS_6362())

		mask = CKCTL_6362_SPI_EN;
@@ -338,7 +338,7 @@ struct clk *clk_get(struct device *dev, const char *id) 
		return &clk_xtm;

	if (!strcmp(id, "periph"))

		return &clk_periph;

	if (BCMCPU_IS_6358() && !strcmp(id, "pcm"))

	if ((BCMCPU_IS_3368() || BCMCPU_IS_6358()) && !strcmp(id, "pcm"))

		return &clk_pcm;

	if ((BCMCPU_IS_6362() || BCMCPU_IS_6368()) && !strcmp(id, "ipsec"))

		return &clk_ipsec;

arch/mips/bcm63xx/cpu.c

+25 −3
Original line number Diff line number Diff line
@@ -29,6 +29,14 @@ static u8 bcm63xx_cpu_rev; 
static unsigned int bcm63xx_cpu_freq;

static unsigned int bcm63xx_memory_size;



static const unsigned long bcm3368_regs_base[] = {

	__GEN_CPU_REGS_TABLE(3368)

};



static const int bcm3368_irqs[] = {

	__GEN_CPU_IRQ_TABLE(3368)

};



static const unsigned long bcm6328_regs_base[] = {

	__GEN_CPU_REGS_TABLE(6328)

};
@@ -116,6 +124,9 @@ unsigned int bcm63xx_get_memory_size(void) 
static unsigned int detect_cpu_clock(void)

{

	switch (bcm63xx_get_cpu_id()) {

	case BCM3368_CPU_ID:

		return 300000000;



	case BCM6328_CPU_ID:

	{

		unsigned int tmp, mips_pll_fcvo;
@@ -266,7 +277,7 @@ static unsigned int detect_memory_size(void) 
		banks = (val & SDRAM_CFG_BANK_MASK) ? 2 : 1;

	}



	if (BCMCPU_IS_6358() || BCMCPU_IS_6368()) {

	if (BCMCPU_IS_3368() || BCMCPU_IS_6358() || BCMCPU_IS_6368()) {

		val = bcm_memc_readl(MEMC_CFG_REG);

		rows = (val & MEMC_CFG_ROW_MASK) >> MEMC_CFG_ROW_SHIFT;

		cols = (val & MEMC_CFG_COL_MASK) >> MEMC_CFG_COL_SHIFT;
@@ -302,12 +313,19 @@ void __init bcm63xx_cpu_init(void) 
		chipid_reg = BCM_6345_PERF_BASE;

		break;

	case CPU_BMIPS4350:

		if ((read_c0_prid() & 0xf0) == 0x10)

		switch ((read_c0_prid() & 0xff)) {

		case 0x04:

			chipid_reg = BCM_3368_PERF_BASE;

			break;

		case 0x10:

			chipid_reg = BCM_6345_PERF_BASE;

		else

			break;

		default:

			chipid_reg = BCM_6368_PERF_BASE;

			break;

		}

		break;

	}



	/*

	 * really early to panic, but delaying panic would not help since we
@@ -322,6 +340,10 @@ void __init bcm63xx_cpu_init(void) 
	bcm63xx_cpu_rev = (tmp & REV_REVID_MASK) >> REV_REVID_SHIFT;



	switch (bcm63xx_cpu_id) {

	case BCM3368_CPU_ID:

		bcm63xx_regs_base = bcm3368_regs_base;

		bcm63xx_irqs = bcm3368_irqs;

		break;

	case BCM6328_CPU_ID:

		bcm63xx_regs_base = bcm6328_regs_base;

		bcm63xx_irqs = bcm6328_irqs;

arch/mips/bcm63xx/dev-flash.c

+1 −0
Original line number Diff line number Diff line
@@ -71,6 +71,7 @@ static int __init bcm63xx_detect_flash_type(void) 
	case BCM6348_CPU_ID:

		/* no way to auto detect so assume parallel */

		return BCM63XX_FLASH_TYPE_PARALLEL;

	case BCM3368_CPU_ID:

	case BCM6358_CPU_ID:

		val = bcm_gpio_readl(GPIO_STRAPBUS_REG);

		if (val & STRAPBUS_6358_BOOT_SEL_PARALLEL)

arch/mips/bcm63xx/dev-spi.c

+4 −2
Original line number Diff line number Diff line
@@ -37,7 +37,8 @@ static __init void bcm63xx_spi_regs_init(void) 
{

	if (BCMCPU_IS_6338() || BCMCPU_IS_6348())

		bcm63xx_regs_spi = bcm6348_regs_spi;

	if (BCMCPU_IS_6358() || BCMCPU_IS_6362() || BCMCPU_IS_6368())

	if (BCMCPU_IS_3368() || BCMCPU_IS_6358() ||

		BCMCPU_IS_6362() || BCMCPU_IS_6368())

		bcm63xx_regs_spi = bcm6358_regs_spi;

}

#else
@@ -87,7 +88,8 @@ int __init bcm63xx_spi_register(void) 
		spi_pdata.msg_ctl_width = SPI_6348_MSG_CTL_WIDTH;

	}



	if (BCMCPU_IS_6358() || BCMCPU_IS_6362() || BCMCPU_IS_6368()) {

	if (BCMCPU_IS_3368() || BCMCPU_IS_6358() || BCMCPU_IS_6362() ||

		BCMCPU_IS_6368()) {

		spi_resources[0].end += BCM_6358_RSET_SPI_SIZE - 1;

		spi_pdata.fifo_size = SPI_6358_MSG_DATA_SIZE;

		spi_pdata.msg_type_shift = SPI_6358_MSG_TYPE_SHIFT;