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Commit 7b2e1277 authored by Laurent Pinchart's avatar Laurent Pinchart
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ARM: OMAP3: clock: Back-propagate rate change from cam_mclk to dpll4_m5 



The cam_mclk clock is generated through the following clocks chain:

dpll4 -> dpll4_m5 -> dpll4_m5x2 -> cam_mclk

As dpll4_m5 and dpll4_m5x2 do not driver any clock other than cam_mclk,
back-propagate the cam_clk rate changes up to dpll4_m5.

Signed-off-by: default avatarLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: default avatarMike Turquette <mturquette@linaro.org>
Acked-by: default avatarSakari Ailus <sakari.ailus@iki.fi>
Tested-by: default avatarSakari Ailus <sakari.ailus@iki.fi>
parent 7d1f9aef

arch/arm/mach-omap2/cclock3xxx_data.c

+9 −1
Original line number Diff line number Diff line
@@ -426,6 +426,7 @@ static struct clk dpll4_m5x2_ck_3630 = { 
	.parent_names	= dpll4_m5x2_ck_parent_names,

	.num_parents	= ARRAY_SIZE(dpll4_m5x2_ck_parent_names),

	.ops		= &dpll4_m5x2_ck_3630_ops,

	.flags		= CLK_SET_RATE_PARENT,

};



static struct clk cam_mclk;
@@ -443,7 +444,14 @@ static struct clk_hw_omap cam_mclk_hw = { 
	.clkdm_name	= "cam_clkdm",

};



DEFINE_STRUCT_CLK(cam_mclk, cam_mclk_parent_names, aes2_ick_ops);

static struct clk cam_mclk = {

	.name		= "cam_mclk",

	.hw		= &cam_mclk_hw.hw,

	.parent_names	= cam_mclk_parent_names,

	.num_parents	= ARRAY_SIZE(cam_mclk_parent_names),

	.ops		= &aes2_ick_ops,

	.flags		= CLK_SET_RATE_PARENT,

};



static const struct clksel_rate clkout2_src_core_rates[] = {

	{ .div = 1, .val = 0, .flags = RATE_IN_3XXX },