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Commit 7b141a87 authored by Veera Sundaram Sankaran's avatar Veera Sundaram Sankaran
Browse files

msm: mdss: remove obsolete hw revision checks



Remove all hw revision checks related to REV_200 from
mdp driver.

Change-Id: I31c18b9c91eb93946f777a4b276aec6c999dd337
Signed-off-by: default avatarVeera Sundaram Sankaran <veeras@codeaurora.org>
parent b245a027
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+4 −30
Original line number Diff line number Diff line
@@ -3496,20 +3496,6 @@ static void mdss_mdp_mixer_update_pipe_map(struct mdss_mdp_ctl *master_ctl,
	mixer->pipe_mapped = mixer->next_pipe_map;
}

static inline u32 mdss_mdp_mpq_pipe_num_map(u32 pipe_num)
{
	u32 mpq_num;
	if (pipe_num == MDSS_MDP_SSPP_VIG3)
		mpq_num = MDSS_MDP_SSPP_VIG2 + 1;
	else if (pipe_num == MDSS_MDP_SSPP_RGB0)
		mpq_num = MDSS_MDP_SSPP_VIG2 + 2;
	else if (pipe_num == MDSS_MDP_SSPP_RGB1)
		mpq_num = MDSS_MDP_SSPP_VIG2 + 3;
	else
		mpq_num = pipe_num;
	return mpq_num;
}

void mdss_mdp_set_roi(struct mdss_mdp_ctl *ctl,
	struct mdss_rect *l_roi, struct mdss_rect *r_roi)
{
@@ -3541,7 +3527,7 @@ static void mdss_mdp_mixer_setup(struct mdss_mdp_ctl *master_ctl,
{
	int i;
	int stage, screen_state, outsize;
	u32 off, blend_op, blend_stage, mpq_num;
	u32 off, blend_op, blend_stage;
	u32 mixercfg = 0, mixer_op_mode = 0, bg_alpha_enable = 0,
	    mixercfg_extn = 0;
	u32 fg_alpha = 0, bg_alpha = 0;
@@ -3586,10 +3572,7 @@ static void mdss_mdp_mixer_setup(struct mdss_mdp_ctl *master_ctl,
	if (pipe == NULL) {
		mixercfg = MDSS_MDP_LM_BORDER_COLOR;
	} else {
		if (mdata->mdp_rev == MDSS_MDP_HW_REV_200) {
			mpq_num = mdss_mdp_mpq_pipe_num_map(pipe->num);
			mixercfg = 1 << (3 * mpq_num);
		} else if (pipe->num == MDSS_MDP_SSPP_VIG3 ||
		if (pipe->num == MDSS_MDP_SSPP_VIG3 ||
			pipe->num == MDSS_MDP_SSPP_RGB3) {
			/* Add 2 to account for Cursor & Border bits */
			mixercfg = 1 << ((3 * pipe->num)+2);
@@ -3697,10 +3680,7 @@ static void mdss_mdp_mixer_setup(struct mdss_mdp_ctl *master_ctl,
		if (!pipe->src_fmt->alpha_enable && bg_alpha_enable)
			mixer_op_mode = 0;

		if (mdata->mdp_rev == MDSS_MDP_HW_REV_200) {
			mpq_num = mdss_mdp_mpq_pipe_num_map(pipe->num);
			mixercfg |= stage << (3 * mpq_num);
		} else if ((stage < MDSS_MDP_STAGE_6) &&
		if ((stage < MDSS_MDP_STAGE_6) &&
			(pipe->num == MDSS_MDP_SSPP_VIG3 ||
			 pipe->num == MDSS_MDP_SSPP_RGB3)) {
			/*
@@ -4011,7 +3991,6 @@ int mdss_mdp_mixer_pipe_update(struct mdss_mdp_pipe *pipe,
{
	struct mdss_mdp_ctl *ctl;
	int i, j, k;
	u32 mpq_num;

	if (!pipe)
		return -EINVAL;
@@ -4064,12 +4043,7 @@ int mdss_mdp_mixer_pipe_update(struct mdss_mdp_pipe *pipe,
		}
	}

	if (ctl->mdata->mdp_rev == MDSS_MDP_HW_REV_200) {
		mpq_num = mdss_mdp_mpq_pipe_num_map(pipe->num);
		ctl->flush_bits |= BIT(mpq_num);
	} else {
	ctl->flush_bits |= mdss_mdp_get_pipe_flush_bits(pipe);
	}

	mutex_unlock(&ctl->flush_lock);

+0 −5
Original line number Diff line number Diff line
@@ -2012,11 +2012,6 @@ static int mdss_mdp_src_addr_setup(struct mdss_mdp_pipe *pipe,
	mdss_mdp_pipe_write(pipe, MDSS_MDP_REG_SSPP_SRC2_ADDR, data.p[2].addr);
	mdss_mdp_pipe_write(pipe, MDSS_MDP_REG_SSPP_SRC3_ADDR, data.p[3].addr);

	/* Flush Sel register only exists in mpq */
	if ((mdata->mdp_rev == MDSS_MDP_HW_REV_200) &&
		(pipe->flags & MDP_VPU_PIPE))
		mdss_mdp_pipe_write(pipe, MDSS_MDP_REG_VIG_FLUSH_SEL, 0);

	return 0;
}