Loading arch/mips/Kconfig +1 −7 Original line number Diff line number Diff line Loading @@ -91,15 +91,8 @@ config BCM47XX select DMA_NONCOHERENT select HW_HAS_PCI select IRQ_CPU select SYS_HAS_CPU_MIPS32_R1 select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_LITTLE_ENDIAN select SSB select SSB_DRIVER_MIPS select SSB_DRIVER_EXTIF select SSB_EMBEDDED select SSB_B43_PCI_BRIDGE if PCI select SSB_PCICORE_HOSTMODE if PCI select GENERIC_GPIO select SYS_HAS_EARLY_PRINTK select CFE Loading Loading @@ -788,6 +781,7 @@ endchoice source "arch/mips/alchemy/Kconfig" source "arch/mips/ath79/Kconfig" source "arch/mips/bcm47xx/Kconfig" source "arch/mips/bcm63xx/Kconfig" source "arch/mips/jazz/Kconfig" source "arch/mips/jz4740/Kconfig" Loading arch/mips/bcm47xx/Kconfig 0 → 100644 +31 −0 Original line number Diff line number Diff line if BCM47XX config BCM47XX_SSB bool "SSB Support for Broadcom BCM47XX" select SYS_HAS_CPU_MIPS32_R1 select SSB select SSB_DRIVER_MIPS select SSB_DRIVER_EXTIF select SSB_EMBEDDED select SSB_B43_PCI_BRIDGE if PCI select SSB_PCICORE_HOSTMODE if PCI default y help Add support for old Broadcom BCM47xx boards with Sonics Silicon Backplane support. This will generate an image with support for SSB and MIPS32 R1 instruction set. config BCM47XX_BCMA bool "BCMA Support for Broadcom BCM47XX" select SYS_HAS_CPU_MIPS32_R2 select BCMA select BCMA_HOST_SOC select BCMA_DRIVER_MIPS select BCMA_DRIVER_PCI_HOSTMODE if PCI default y help Add support for new Broadcom BCM47xx boards with Broadcom specific Advanced Microcontroller Bus. This will generate an image with support for BCMA and MIPS32 R2 instruction set. endif arch/mips/bcm47xx/Makefile +2 −1 Original line number Diff line number Diff line Loading @@ -3,4 +3,5 @@ # under Linux. # obj-y := gpio.o irq.o nvram.o prom.o serial.o setup.o time.o wgt634u.o obj-y += gpio.o irq.o nvram.o prom.o serial.o setup.o time.o obj-$(CONFIG_BCM47XX_SSB) += wgt634u.o arch/mips/bcm47xx/gpio.c +61 −21 Original line number Diff line number Diff line Loading @@ -20,11 +20,14 @@ static DECLARE_BITMAP(gpio_in_use, BCM47XX_EXTIF_GPIO_LINES); int gpio_request(unsigned gpio, const char *tag) { if (ssb_chipco_available(&ssb_bcm47xx.chipco) && switch (bcm47xx_bus_type) { #ifdef CONFIG_BCM47XX_SSB case BCM47XX_BUS_TYPE_SSB: if (ssb_chipco_available(&bcm47xx_bus.ssb.chipco) && ((unsigned)gpio >= BCM47XX_CHIPCO_GPIO_LINES)) return -EINVAL; if (ssb_extif_available(&ssb_bcm47xx.extif) && if (ssb_extif_available(&bcm47xx_bus.ssb.extif) && ((unsigned)gpio >= BCM47XX_EXTIF_GPIO_LINES)) return -EINVAL; Loading @@ -32,30 +35,67 @@ int gpio_request(unsigned gpio, const char *tag) return -EBUSY; return 0; #endif #ifdef CONFIG_BCM47XX_BCMA case BCM47XX_BUS_TYPE_BCMA: if (gpio >= BCM47XX_CHIPCO_GPIO_LINES) return -EINVAL; if (test_and_set_bit(gpio, gpio_in_use)) return -EBUSY; return 0; #endif } return -EINVAL; } EXPORT_SYMBOL(gpio_request); void gpio_free(unsigned gpio) { if (ssb_chipco_available(&ssb_bcm47xx.chipco) && switch (bcm47xx_bus_type) { #ifdef CONFIG_BCM47XX_SSB case BCM47XX_BUS_TYPE_SSB: if (ssb_chipco_available(&bcm47xx_bus.ssb.chipco) && ((unsigned)gpio >= BCM47XX_CHIPCO_GPIO_LINES)) return; if (ssb_extif_available(&ssb_bcm47xx.extif) && if (ssb_extif_available(&bcm47xx_bus.ssb.extif) && ((unsigned)gpio >= BCM47XX_EXTIF_GPIO_LINES)) return; clear_bit(gpio, gpio_in_use); return; #endif #ifdef CONFIG_BCM47XX_BCMA case BCM47XX_BUS_TYPE_BCMA: if (gpio >= BCM47XX_CHIPCO_GPIO_LINES) return; clear_bit(gpio, gpio_in_use); return; #endif } } EXPORT_SYMBOL(gpio_free); int gpio_to_irq(unsigned gpio) { if (ssb_chipco_available(&ssb_bcm47xx.chipco)) return ssb_mips_irq(ssb_bcm47xx.chipco.dev) + 2; else if (ssb_extif_available(&ssb_bcm47xx.extif)) return ssb_mips_irq(ssb_bcm47xx.extif.dev) + 2; switch (bcm47xx_bus_type) { #ifdef CONFIG_BCM47XX_SSB case BCM47XX_BUS_TYPE_SSB: if (ssb_chipco_available(&bcm47xx_bus.ssb.chipco)) return ssb_mips_irq(bcm47xx_bus.ssb.chipco.dev) + 2; else if (ssb_extif_available(&bcm47xx_bus.ssb.extif)) return ssb_mips_irq(bcm47xx_bus.ssb.extif.dev) + 2; else return -EINVAL; #endif #ifdef CONFIG_BCM47XX_BCMA case BCM47XX_BUS_TYPE_BCMA: return bcma_core_mips_irq(bcm47xx_bus.bcma.bus.drv_cc.core) + 2; #endif } return -EINVAL; } EXPORT_SYMBOL_GPL(gpio_to_irq); arch/mips/bcm47xx/irq.c +12 −0 Original line number Diff line number Diff line Loading @@ -26,6 +26,7 @@ #include <linux/interrupt.h> #include <linux/irq.h> #include <asm/irq_cpu.h> #include <bcm47xx.h> void plat_irq_dispatch(void) { Loading @@ -51,5 +52,16 @@ void plat_irq_dispatch(void) void __init arch_init_irq(void) { #ifdef CONFIG_BCM47XX_BCMA if (bcm47xx_bus_type == BCM47XX_BUS_TYPE_BCMA) { bcma_write32(bcm47xx_bus.bcma.bus.drv_mips.core, BCMA_MIPS_MIPS74K_INTMASK(5), 1 << 31); /* * the kernel reads the timer irq from some register and thinks * it's #5, but we offset it by 2 and route to #7 */ cp0_compare_irq = 7; } #endif mips_cpu_irq_init(); } Loading
arch/mips/Kconfig +1 −7 Original line number Diff line number Diff line Loading @@ -91,15 +91,8 @@ config BCM47XX select DMA_NONCOHERENT select HW_HAS_PCI select IRQ_CPU select SYS_HAS_CPU_MIPS32_R1 select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_LITTLE_ENDIAN select SSB select SSB_DRIVER_MIPS select SSB_DRIVER_EXTIF select SSB_EMBEDDED select SSB_B43_PCI_BRIDGE if PCI select SSB_PCICORE_HOSTMODE if PCI select GENERIC_GPIO select SYS_HAS_EARLY_PRINTK select CFE Loading Loading @@ -788,6 +781,7 @@ endchoice source "arch/mips/alchemy/Kconfig" source "arch/mips/ath79/Kconfig" source "arch/mips/bcm47xx/Kconfig" source "arch/mips/bcm63xx/Kconfig" source "arch/mips/jazz/Kconfig" source "arch/mips/jz4740/Kconfig" Loading
arch/mips/bcm47xx/Kconfig 0 → 100644 +31 −0 Original line number Diff line number Diff line if BCM47XX config BCM47XX_SSB bool "SSB Support for Broadcom BCM47XX" select SYS_HAS_CPU_MIPS32_R1 select SSB select SSB_DRIVER_MIPS select SSB_DRIVER_EXTIF select SSB_EMBEDDED select SSB_B43_PCI_BRIDGE if PCI select SSB_PCICORE_HOSTMODE if PCI default y help Add support for old Broadcom BCM47xx boards with Sonics Silicon Backplane support. This will generate an image with support for SSB and MIPS32 R1 instruction set. config BCM47XX_BCMA bool "BCMA Support for Broadcom BCM47XX" select SYS_HAS_CPU_MIPS32_R2 select BCMA select BCMA_HOST_SOC select BCMA_DRIVER_MIPS select BCMA_DRIVER_PCI_HOSTMODE if PCI default y help Add support for new Broadcom BCM47xx boards with Broadcom specific Advanced Microcontroller Bus. This will generate an image with support for BCMA and MIPS32 R2 instruction set. endif
arch/mips/bcm47xx/Makefile +2 −1 Original line number Diff line number Diff line Loading @@ -3,4 +3,5 @@ # under Linux. # obj-y := gpio.o irq.o nvram.o prom.o serial.o setup.o time.o wgt634u.o obj-y += gpio.o irq.o nvram.o prom.o serial.o setup.o time.o obj-$(CONFIG_BCM47XX_SSB) += wgt634u.o
arch/mips/bcm47xx/gpio.c +61 −21 Original line number Diff line number Diff line Loading @@ -20,11 +20,14 @@ static DECLARE_BITMAP(gpio_in_use, BCM47XX_EXTIF_GPIO_LINES); int gpio_request(unsigned gpio, const char *tag) { if (ssb_chipco_available(&ssb_bcm47xx.chipco) && switch (bcm47xx_bus_type) { #ifdef CONFIG_BCM47XX_SSB case BCM47XX_BUS_TYPE_SSB: if (ssb_chipco_available(&bcm47xx_bus.ssb.chipco) && ((unsigned)gpio >= BCM47XX_CHIPCO_GPIO_LINES)) return -EINVAL; if (ssb_extif_available(&ssb_bcm47xx.extif) && if (ssb_extif_available(&bcm47xx_bus.ssb.extif) && ((unsigned)gpio >= BCM47XX_EXTIF_GPIO_LINES)) return -EINVAL; Loading @@ -32,30 +35,67 @@ int gpio_request(unsigned gpio, const char *tag) return -EBUSY; return 0; #endif #ifdef CONFIG_BCM47XX_BCMA case BCM47XX_BUS_TYPE_BCMA: if (gpio >= BCM47XX_CHIPCO_GPIO_LINES) return -EINVAL; if (test_and_set_bit(gpio, gpio_in_use)) return -EBUSY; return 0; #endif } return -EINVAL; } EXPORT_SYMBOL(gpio_request); void gpio_free(unsigned gpio) { if (ssb_chipco_available(&ssb_bcm47xx.chipco) && switch (bcm47xx_bus_type) { #ifdef CONFIG_BCM47XX_SSB case BCM47XX_BUS_TYPE_SSB: if (ssb_chipco_available(&bcm47xx_bus.ssb.chipco) && ((unsigned)gpio >= BCM47XX_CHIPCO_GPIO_LINES)) return; if (ssb_extif_available(&ssb_bcm47xx.extif) && if (ssb_extif_available(&bcm47xx_bus.ssb.extif) && ((unsigned)gpio >= BCM47XX_EXTIF_GPIO_LINES)) return; clear_bit(gpio, gpio_in_use); return; #endif #ifdef CONFIG_BCM47XX_BCMA case BCM47XX_BUS_TYPE_BCMA: if (gpio >= BCM47XX_CHIPCO_GPIO_LINES) return; clear_bit(gpio, gpio_in_use); return; #endif } } EXPORT_SYMBOL(gpio_free); int gpio_to_irq(unsigned gpio) { if (ssb_chipco_available(&ssb_bcm47xx.chipco)) return ssb_mips_irq(ssb_bcm47xx.chipco.dev) + 2; else if (ssb_extif_available(&ssb_bcm47xx.extif)) return ssb_mips_irq(ssb_bcm47xx.extif.dev) + 2; switch (bcm47xx_bus_type) { #ifdef CONFIG_BCM47XX_SSB case BCM47XX_BUS_TYPE_SSB: if (ssb_chipco_available(&bcm47xx_bus.ssb.chipco)) return ssb_mips_irq(bcm47xx_bus.ssb.chipco.dev) + 2; else if (ssb_extif_available(&bcm47xx_bus.ssb.extif)) return ssb_mips_irq(bcm47xx_bus.ssb.extif.dev) + 2; else return -EINVAL; #endif #ifdef CONFIG_BCM47XX_BCMA case BCM47XX_BUS_TYPE_BCMA: return bcma_core_mips_irq(bcm47xx_bus.bcma.bus.drv_cc.core) + 2; #endif } return -EINVAL; } EXPORT_SYMBOL_GPL(gpio_to_irq);
arch/mips/bcm47xx/irq.c +12 −0 Original line number Diff line number Diff line Loading @@ -26,6 +26,7 @@ #include <linux/interrupt.h> #include <linux/irq.h> #include <asm/irq_cpu.h> #include <bcm47xx.h> void plat_irq_dispatch(void) { Loading @@ -51,5 +52,16 @@ void plat_irq_dispatch(void) void __init arch_init_irq(void) { #ifdef CONFIG_BCM47XX_BCMA if (bcm47xx_bus_type == BCM47XX_BUS_TYPE_BCMA) { bcma_write32(bcm47xx_bus.bcma.bus.drv_mips.core, BCMA_MIPS_MIPS74K_INTMASK(5), 1 << 31); /* * the kernel reads the timer irq from some register and thinks * it's #5, but we offset it by 2 and route to #7 */ cp0_compare_irq = 7; } #endif mips_cpu_irq_init(); }