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Commit 7a54698f authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'dt-3.13-4' of git://git.infradead.org/linux-mvebu into next/dt 

From Jason Cooper, mvebu dt changes for v3.13 (round 4):

 - mvebu
    - core divider clock driver dt binding and nodes

* tag 'dt-3.13-4' of git://git.infradead.org/linux-mvebu:
  ARM: mvebu: Add the core-divider clock to Armada 370/XP
  ARM: mvebu: Add a 2 GHz fixed-clock Armada 370/XP
  ARM: mvebu: Add Core Divider clock device-tree binding
parents 0f564380 f039dfb5

Documentation/devicetree/bindings/clock/mvebu-corediv-clock.txt

0 → 100644
+19 −0
Original line number Diff line number Diff line 
* Core Divider Clock bindings for Marvell MVEBU SoCs



The following is a list of provided IDs and clock names on Armada 370/XP:

 0 = nand (NAND clock)



Required properties:

- compatible : must be "marvell,armada-370-corediv-clock"

- reg : must be the register address of Core Divider control register

- #clock-cells : from common clock binding; shall be set to 1

- clocks : must be set to the parent's phandle



Example:



corediv_clk: corediv-clocks@18740 {

	compatible = "marvell,armada-370-corediv-clock";

	reg = <0x18740 0xc>;

	#clock-cells = <1>;

	clocks = <&pll>;

};

arch/arm/boot/dts/armada-370-xp.dtsi

+17 −0
Original line number Diff line number Diff line
@@ -138,6 +138,14 @@ 
				status = "disabled";

			};



			coredivclk: corediv-clock@18740 {

				compatible = "marvell,armada-370-corediv-clock";

				reg = <0x18740 0xc>;

				#clock-cells = <1>;

				clocks = <&mainpll>;

				clock-output-names = "nand";

			};



			timer@20300 {

				reg = <0x20300 0x30>, <0x21040 0x30>;

				interrupts = <37>, <38>, <39>, <40>, <5>, <6>;
@@ -251,4 +259,13 @@ 


		};

	};



	clocks {

		/* 2 GHz fixed main PLL */

		mainpll: mainpll {

			compatible = "fixed-clock";

			#clock-cells = <0>;

			clock-frequency = <2000000000>;

		};

	};

 };