Loading arch/arm/boot/dts/qcom/mdmcalifornium-coresight.dtsi +0 −14 Original line number Diff line number Diff line Loading @@ -400,20 +400,6 @@ clock-names = "core_clk", "core_a_clk"; }; cti_modem_cpu0: cti@8390000 { compatible = "arm,coresight-cti"; reg = <0x8390000 0x1000>; reg-names = "cti-base"; coresight-id = <25>; coresight-name = "coresight-cti-modem-cpu0"; coresight-nr-inports = <0>; clocks = <&clock_gcc clk_qdss_clk>, <&clock_gcc clk_qdss_a_clk>; clock-names = "core_clk", "core_a_clk"; }; cti_pmu_cpu0: cti@841000 { compatible = "arm,coresight-cti"; reg = <0x841000 0x1000>; Loading Loading
arch/arm/boot/dts/qcom/mdmcalifornium-coresight.dtsi +0 −14 Original line number Diff line number Diff line Loading @@ -400,20 +400,6 @@ clock-names = "core_clk", "core_a_clk"; }; cti_modem_cpu0: cti@8390000 { compatible = "arm,coresight-cti"; reg = <0x8390000 0x1000>; reg-names = "cti-base"; coresight-id = <25>; coresight-name = "coresight-cti-modem-cpu0"; coresight-nr-inports = <0>; clocks = <&clock_gcc clk_qdss_clk>, <&clock_gcc clk_qdss_a_clk>; clock-names = "core_clk", "core_a_clk"; }; cti_pmu_cpu0: cti@841000 { compatible = "arm,coresight-cti"; reg = <0x841000 0x1000>; Loading