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Commit 7861ab55 authored by Charan Teja Reddy's avatar Charan Teja Reddy
Browse files

ARM: dts: msm: add DCC device node on msmtitanium 



Add device node to support Data Capture and Compare block on
msmtitanium.

Change-Id: I385a4378ea53745bca88f272fa7659f3a04723b8
Signed-off-by: default avatarCharan Teja Reddy <charante@codeaurora.org>
parent 0a1fa0b8

arch/arm/boot/dts/qcom/msmtitanium-coresight.dtsi

+37 −0
Original line number Diff line number Diff line
@@ -729,4 +729,41 @@ 
			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	tpda: tpda@6003000 {

		compatible = "qcom,coresight-tpda";

		reg = <0x6003000 0x1000>;

		reg-names = "tpda-base";



		coresight-id = <45>;

		coresight-name = "coresight-tpda";

		coresight-nr-inports = <2>;

		coresight-outports = <0>;

		coresight-child-list = <&funnel_in0>;

		coresight-child-ports = <6>;



		qcom,tpda-atid = <64>;

		qcom,cmb-elem-size = <0 32>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	tpdm_dcc: tpdm@6110000 {

		compatible = "qcom,coresight-tpdm";

		reg = <0x6110000 0x1000>;

		reg-names = "tpdm-base";



		coresight-id = <46>;

		coresight-name = "coresight-tpdm-dcc";

		coresight-nr-inports = <1>;

		coresight-outports = <0>;

		coresight-child-list = <&tpda>;

		coresight-child-ports = <0>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};

};

arch/arm/boot/dts/qcom/msmtitanium.dtsi

+12 −0
Original line number Diff line number Diff line
@@ -208,6 +208,18 @@ 
		#clock-cells = <1>;

	};



	dcc: dcc@b3000 {

		compatible = "qcom,dcc";

		reg = <0xb3000 0x1000>,

		      <0xb4000 0x2000>;

		reg-names = "dcc-base", "dcc-ram-base";



		clocks = <&clock_gcc clk_gcc_dcc_clk>;

		clock-names = "dcc_clk";



		qcom,save-reg;

	};



	qcom,ipc-spinlock@1905000 {

		compatible = "qcom,ipc-spinlock-sfpb";

		reg = <0x1905000 0x8000>;