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Commit 785e3268 authored by Manuel Lauss's avatar Manuel Lauss Committed by Ralf Baechle
Browse files

MIPS: Alchemy: update core interrupt code. 



This patch attempts to modernize core Alchemy interrupt handling code.

- add irq_chips for irq controllers instead of irq type,
- add a set_type() hook to change irq trigger type during runtime,
- add a set_wake() hook to control GPIO0..7 based wakeup,
- use linux' IRQF_TRIGGER_ constants instead of homebrew ones,
- enable GENERIC_HARDIRQS_NO__DO_IRQ.
- simplify plat_irq_dispatch
- merge au1xxx_irqmap into irq.c file, the only place where its
  contents are referenced.
- board_init_irq() is now mandatory for every board; use it to register
  the remaining (gpio-based) interrupt sources; update all boards
  accordingly.

Run-tested on Db1200 and other Au1200 based platforms.

Signed-off-by: default avatarManuel Lauss <mano@roarinelk.homelinux.net>
Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>

 delete mode 100644 arch/mips/alchemy/common/au1xxx_irqmap.c
parent 7179380e

arch/mips/alchemy/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -134,3 +134,4 @@ config SOC_AU1X00 
	select SYS_HAS_CPU_MIPS32_R1

	select SYS_SUPPORTS_32BIT_KERNEL

	select SYS_SUPPORTS_APM_EMULATION

	select GENERIC_HARDIRQS_NO__DO_IRQ

arch/mips/alchemy/common/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -6,7 +6,7 @@ 
#



obj-y += prom.o irq.o puts.o time.o reset.o \

	au1xxx_irqmap.o clocks.o platform.o power.o setup.o \

	clocks.o platform.o power.o setup.o \

	sleeper.o cputable.o dma.o dbdma.o gpio.o



obj-$(CONFIG_PCI)		+= pci.o

arch/mips/alchemy/common/au1xxx_irqmap.c

deleted100644 → 0
+0 −205
Original line number Diff line number Diff line 
/*

 * BRIEF MODULE DESCRIPTION

 *	Au1xxx processor specific IRQ tables

 *

 * Copyright 2004 Embedded Edge, LLC

 *	dan@embeddededge.com

 *

 *  This program is free software; you can redistribute	 it and/or modify it

 *  under  the terms of	 the GNU General  Public License as published by the

 *  Free Software Foundation;  either version 2 of the	License, or (at your

 *  option) any later version.

 *

 *  THIS  SOFTWARE  IS PROVIDED	  ``AS	IS'' AND   ANY	EXPRESS OR IMPLIED

 *  WARRANTIES,	  INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF

 *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN

 *  NO	EVENT  SHALL   THE AUTHOR  BE	 LIABLE FOR ANY	  DIRECT, INDIRECT,

 *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT

 *  NOT LIMITED	  TO, PROCUREMENT OF  SUBSTITUTE GOODS	OR SERVICES; LOSS OF

 *  USE, DATA,	OR PROFITS; OR	BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON

 *  ANY THEORY OF LIABILITY, WHETHER IN	 CONTRACT, STRICT LIABILITY, OR TORT

 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF

 *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 *

 *  You should have received a copy of the  GNU General Public License along

 *  with this program; if not, write  to the Free Software Foundation, Inc.,

 *  675 Mass Ave, Cambridge, MA 02139, USA.

 */

#include <linux/init.h>

#include <linux/kernel.h>



#include <au1000.h>



/* The IC0 interrupt table.  This is processor, rather than

 * board dependent, so no reason to keep this info in the board

 * dependent files.

 *

 * Careful if you change match 2 request!

 * The interrupt handler is called directly from the low level dispatch code.

 */

struct au1xxx_irqmap __initdata au1xxx_ic0_map[] = {



#if defined(CONFIG_SOC_AU1000)

	{ AU1000_UART0_INT, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1000_UART1_INT, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1000_UART2_INT, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1000_UART3_INT, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1000_SSI0_INT, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1000_SSI1_INT, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1000_DMA_INT_BASE, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1000_DMA_INT_BASE+1, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1000_DMA_INT_BASE+2, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1000_DMA_INT_BASE+3, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1000_DMA_INT_BASE+4, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1000_DMA_INT_BASE+5, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1000_DMA_INT_BASE+6, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1000_DMA_INT_BASE+7, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1000_TOY_INT, INTC_INT_RISE_EDGE, 0 },

	{ AU1000_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },

	{ AU1000_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },

	{ AU1000_TOY_MATCH2_INT, INTC_INT_RISE_EDGE, 1 },

	{ AU1000_RTC_INT, INTC_INT_RISE_EDGE, 0 },

	{ AU1000_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },

	{ AU1000_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },

	{ AU1000_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 },

	{ AU1000_IRDA_TX_INT, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1000_IRDA_RX_INT, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1000_USB_DEV_REQ_INT, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1000_USB_DEV_SUS_INT, INTC_INT_RISE_EDGE, 0 },

	{ AU1000_USB_HOST_INT, INTC_INT_LOW_LEVEL, 0 },

	{ AU1000_ACSYNC_INT, INTC_INT_RISE_EDGE, 0 },

	{ AU1000_MAC0_DMA_INT, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1000_MAC1_DMA_INT, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1000_AC97C_INT, INTC_INT_RISE_EDGE, 0 },



#elif defined(CONFIG_SOC_AU1500)



	{ AU1500_UART0_INT, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1000_PCI_INTA, INTC_INT_LOW_LEVEL, 0 },

	{ AU1000_PCI_INTB, INTC_INT_LOW_LEVEL, 0 },

	{ AU1500_UART3_INT, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1000_PCI_INTC, INTC_INT_LOW_LEVEL, 0 },

	{ AU1000_PCI_INTD, INTC_INT_LOW_LEVEL, 0 },

	{ AU1000_DMA_INT_BASE, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1000_DMA_INT_BASE+1, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1000_DMA_INT_BASE+2, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1000_DMA_INT_BASE+3, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1000_DMA_INT_BASE+4, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1000_DMA_INT_BASE+5, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1000_DMA_INT_BASE+6, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1000_DMA_INT_BASE+7, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1000_TOY_INT, INTC_INT_RISE_EDGE, 0 },

	{ AU1000_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },

	{ AU1000_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },

	{ AU1000_TOY_MATCH2_INT, INTC_INT_RISE_EDGE, 1 },

	{ AU1000_RTC_INT, INTC_INT_RISE_EDGE, 0 },

	{ AU1000_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },

	{ AU1000_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },

	{ AU1000_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 },

	{ AU1000_USB_DEV_REQ_INT, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1000_USB_DEV_SUS_INT, INTC_INT_RISE_EDGE, 0 },

	{ AU1000_USB_HOST_INT, INTC_INT_LOW_LEVEL, 0 },

	{ AU1000_ACSYNC_INT, INTC_INT_RISE_EDGE, 0 },

	{ AU1500_MAC0_DMA_INT, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1500_MAC1_DMA_INT, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1000_AC97C_INT, INTC_INT_RISE_EDGE, 0 },



#elif defined(CONFIG_SOC_AU1100)



	{ AU1100_UART0_INT, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1100_UART1_INT, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1100_SD_INT, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1100_UART3_INT, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1000_SSI0_INT, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1000_SSI1_INT, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1000_DMA_INT_BASE, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1000_DMA_INT_BASE+1, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1000_DMA_INT_BASE+2, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1000_DMA_INT_BASE+3, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1000_DMA_INT_BASE+4, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1000_DMA_INT_BASE+5, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1000_DMA_INT_BASE+6, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1000_DMA_INT_BASE+7, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1000_TOY_INT, INTC_INT_RISE_EDGE, 0 },

	{ AU1000_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },

	{ AU1000_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },

	{ AU1000_TOY_MATCH2_INT, INTC_INT_RISE_EDGE, 1 },

	{ AU1000_RTC_INT, INTC_INT_RISE_EDGE, 0 },

	{ AU1000_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },

	{ AU1000_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },

	{ AU1000_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 },

	{ AU1000_IRDA_TX_INT, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1000_IRDA_RX_INT, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1000_USB_DEV_REQ_INT, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1000_USB_DEV_SUS_INT, INTC_INT_RISE_EDGE, 0 },

	{ AU1000_USB_HOST_INT, INTC_INT_LOW_LEVEL, 0 },

	{ AU1000_ACSYNC_INT, INTC_INT_RISE_EDGE, 0 },

	{ AU1100_MAC0_DMA_INT, INTC_INT_HIGH_LEVEL, 0 },

	/* { AU1000_GPIO215_208_INT, INTC_INT_HIGH_LEVEL, 0 }, */

	{ AU1100_LCD_INT, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1000_AC97C_INT, INTC_INT_RISE_EDGE, 0 },



#elif defined(CONFIG_SOC_AU1550)



	{ AU1550_UART0_INT, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1550_PCI_INTA, INTC_INT_LOW_LEVEL, 0 },

	{ AU1550_PCI_INTB, INTC_INT_LOW_LEVEL, 0 },

	{ AU1550_DDMA_INT, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1550_CRYPTO_INT, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1550_PCI_INTC, INTC_INT_LOW_LEVEL, 0 },

	{ AU1550_PCI_INTD, INTC_INT_LOW_LEVEL, 0 },

	{ AU1550_PCI_RST_INT, INTC_INT_LOW_LEVEL, 0 },

	{ AU1550_UART1_INT, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1550_UART3_INT, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1550_PSC0_INT, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1550_PSC1_INT, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1550_PSC2_INT, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1550_PSC3_INT, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1000_TOY_INT, INTC_INT_RISE_EDGE, 0 },

	{ AU1000_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },

	{ AU1000_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },

	{ AU1000_TOY_MATCH2_INT, INTC_INT_RISE_EDGE, 1 },

	{ AU1000_RTC_INT, INTC_INT_RISE_EDGE, 0 },

	{ AU1000_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },

	{ AU1000_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },

	{ AU1000_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 },

	{ AU1550_NAND_INT, INTC_INT_RISE_EDGE, 0 },

	{ AU1550_USB_DEV_REQ_INT, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1550_USB_DEV_SUS_INT, INTC_INT_RISE_EDGE, 0 },

	{ AU1550_USB_HOST_INT, INTC_INT_LOW_LEVEL, 0 },

	{ AU1550_MAC0_DMA_INT, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1550_MAC1_DMA_INT, INTC_INT_HIGH_LEVEL, 0 },



#elif defined(CONFIG_SOC_AU1200)



	{ AU1200_UART0_INT, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1200_SWT_INT, INTC_INT_RISE_EDGE, 0 },

	{ AU1200_SD_INT, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1200_DDMA_INT, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1200_MAE_BE_INT, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1200_UART1_INT, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1200_MAE_FE_INT, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1200_PSC0_INT, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1200_PSC1_INT, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1200_AES_INT, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1200_CAMERA_INT, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1000_TOY_INT, INTC_INT_RISE_EDGE, 0 },

	{ AU1000_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },

	{ AU1000_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },

	{ AU1000_TOY_MATCH2_INT, INTC_INT_RISE_EDGE, 1 },

	{ AU1000_RTC_INT, INTC_INT_RISE_EDGE, 0 },

	{ AU1000_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },

	{ AU1000_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },

	{ AU1000_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 },

	{ AU1200_NAND_INT, INTC_INT_RISE_EDGE, 0 },

	{ AU1200_USB_INT, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1200_LCD_INT, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1200_MAE_BOTH_INT, INTC_INT_HIGH_LEVEL, 0 },



#else

#error "Error: Unknown Alchemy SOC"

#endif



};



int __initdata au1xxx_ic0_nr_irqs = ARRAY_SIZE(au1xxx_ic0_map);

arch/mips/alchemy/common/irq.c

+422 −363

File changed.

Preview size limit exceeded, changes collapsed.

arch/mips/alchemy/common/power.c

+4 −2
Original line number Diff line number Diff line
@@ -51,7 +51,6 @@ static void au1000_calibrate_delay(void); 


extern unsigned long save_local_and_disable(int controller);

extern void restore_local_and_enable(int controller, unsigned long mask);

extern void local_enable_irq(unsigned int irq_nr);



static DEFINE_SPINLOCK(pm_lock);
@@ -364,7 +363,10 @@ static int pm_do_freq(ctl_table *ctl, int write, struct file *file, 
	 */

	intc0_mask = save_local_and_disable(0);

	intc1_mask = save_local_and_disable(1);

	local_enable_irq(AU1000_TOY_MATCH2_INT);

	val = 1 << (AU1000_TOY_MATCH2_INT - AU1000_INTC0_INT_BASE);

	au_writel(val, IC0_MASKSET);	/* unmask */

	au_writel(val, IC0_WAKESET);	/* enable wake-from-sleep */

	au_sync();

	spin_unlock_irqrestore(&pm_lock, flags);

	au1000_calibrate_delay();

	restore_local_and_enable(0, intc0_mask);