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Commit 782bb5a5 authored by Paul Mundt's avatar Paul Mundt
Browse files

sh: default to extended TLB support. 



All SH-X2 and SH-X3 parts support an extended TLB mode, which has been
left as experimental since support was originally merged. Now that it's
had some time to stabilize and get some exposure to various platforms,
we can drop it as an option and default enable it across the board.

This is also good future proofing for newer parts that will drop support
for the legacy TLB mode completely.

This will also force 3-level page tables for all newer parts, which is
necessary both for the varying page sizes and larger memories.

Signed-off-by: default avatarPaul Mundt <lethal@linux-sh.org>
parent 206582c3

arch/sh/include/asm/pgalloc.h

+1 −1
Original line number Diff line number Diff line
@@ -9,7 +9,7 @@ 
extern pgd_t *pgd_alloc(struct mm_struct *);

extern void pgd_free(struct mm_struct *mm, pgd_t *pgd);



#ifdef CONFIG_PGTABLE_LEVELS_3

#if PAGETABLE_LEVELS > 2

extern void pud_populate(struct mm_struct *mm, pud_t *pudp, pmd_t *pmd);

extern pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long address);

extern void pmd_free(struct mm_struct *mm, pmd_t *pmd);

arch/sh/include/asm/pgtable.h

+1 −1
Original line number Diff line number Diff line
@@ -12,7 +12,7 @@ 
#ifndef __ASM_SH_PGTABLE_H

#define __ASM_SH_PGTABLE_H



#ifdef CONFIG_PGTABLE_LEVELS_3

#ifdef CONFIG_X2TLB

#include <asm/pgtable_pmd.h>

#else

#include <asm/pgtable_nopmd.h>

arch/sh/include/asm/pgtable_nopmd.h

+6 −5
Original line number Diff line number Diff line
@@ -6,6 +6,7 @@ 
/*

 * traditional two-level paging structure

 */

#define PAGETABLE_LEVELS	2



/* PTE bits */

#define PTE_MAGNITUDE		2	/* 32-bit PTEs */

arch/sh/include/asm/pgtable_pmd.h

+3 −2
Original line number Diff line number Diff line
@@ -7,8 +7,9 @@ 
 * Some cores need a 3-level page table layout, for example when using

 * 64-bit PTEs and 4K pages.

 */

#define PAGETABLE_LEVELS	3



#define PTE_MAGNITUDE	3	/* 64-bit PTEs on extended mode SH-X2 TLB */

#define PTE_MAGNITUDE		3	/* 64-bit PTEs on SH-X2 TLB */



/* PGD bits */

#define PGDIR_SHIFT		30

arch/sh/mm/Kconfig

+2 −27
Original line number Diff line number Diff line
@@ -100,13 +100,8 @@ config PMB_LEGACY 
	  and allows systems to support up to 512MiB of system memory.



config X2TLB

	bool "Enable extended TLB mode"

	depends on (CPU_SHX2 || CPU_SHX3) && MMU && EXPERIMENTAL

	help

	  Selecting this option will enable the extended mode of the SH-X2

	  TLB. For legacy SH-X behaviour and interoperability, say N. For

	  all of the fun new features and a willingless to submit bug reports,

	  say Y.

	def_bool y

	depends on (CPU_SHX2 || CPU_SHX3) && MMU



config VSYSCALL

	bool "Support vsyscall page"
@@ -174,32 +169,12 @@ config ARCH_MEMORY_PROBE 
	def_bool y

	depends on MEMORY_HOTPLUG



choice

	prompt "Page table layout"

	default PGTABLE_LEVELS_3 if X2TLB

	default PGTABLE_LEVELS_2



config PGTABLE_LEVELS_2

       bool "2 Levels"

       help

         This is the default page table layout for all SuperH CPUs.



config PGTABLE_LEVELS_3

       bool "3 Levels"

       depends on X2TLB

       help

         This enables a 3 level page table structure.



endchoice



choice

	prompt "Kernel page size"

	default PAGE_SIZE_8KB if X2TLB

	default PAGE_SIZE_4KB



config PAGE_SIZE_4KB

	bool "4kB"

	depends on !MMU || !X2TLB || PGTABLE_LEVELS_3

	help

	  This is the default page size used by all SuperH CPUs.