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Commit 77a62f09 authored by Abhijeet Dharmapurikar's avatar Abhijeet Dharmapurikar Committed by Subbaraman Narayanamurthy
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power: qpnp-smbcharger: configure the start of ICL 



An overshoot in the USB input current is observed during charger
buck startup. The ICL control is not active when the buck starts
and if there is high load the buck pulls as much current as it
needs.

The root cause is that the ICL control is enabled only after soft
start is done, that is when APSD completes.

The fix is to enable ICL as soon as the buck starts switching.
This can be done by configuring ICL to start based on Syson LDO.
Syson LDO is used to power the drivers of the switching FETS and
becomes active right when the buck starts switching.

Also, during OTG, the ICL control buffer requires voltage sourced
from USB mid. On charger insertion, USB mid has 5V before
switching begins however for OTG, USB mid doesn't have 5V until
the boost starts. If ICL control is left at Syson LDO, it will
falsely detect a short circuit and disables boost. The boost will
never start again when this happens. So reset the ICL control to
start upon soft start completion before starting boost mode.

CRs-Fixed: 962458
Change-Id: I48869f3fa04d0f415bd5a7eb201bd86c7339a362
Signed-off-by: default avatarAbhijeet Dharmapurikar <adharmap@codeaurora.org>
Signed-off-by: default avatarSubbaraman Narayanamurthy <subbaram@codeaurora.org>
parent 359d85b4

drivers/power/qpnp-smbcharger.c

+52 −1
Original line number Diff line number Diff line
@@ -304,6 +304,7 @@ enum smbchg_wa { 
	SMBCHG_FLASH_ICL_DISABLE_WA = BIT(5),

	SMBCHG_RESTART_WA = BIT(6),

	SMBCHG_FLASH_BUCK_SWITCH_FREQ_WA = BIT(7),

	SMBCHG_ICL_CONTROL_WA = BIT(8),

};



enum print_reason {
@@ -3164,6 +3165,39 @@ static int smbchg_otg_pulse_skip_disable(struct smbchg_chip *chip, 
	return 0;

}



#define ICL_BUF_CONFIG_REG	0xFC

#define ICL_BUF_CFG_BIT		BIT(2)

#define ICL_BUF_SS_DONE_VAL	0

#define ICL_BUF_SYSON_LDO_VAL	BIT(2)

static int smbchg_configure_icl_buffer(struct smbchg_chip *chip, u8 val)

{

	int rc;



	if ((val != ICL_BUF_SS_DONE_VAL) && (val != ICL_BUF_SYSON_LDO_VAL)) {

		pr_err("Invalid val 0x%02x\n", val);

		return -EINVAL;

	}



	rc = smbchg_sec_masked_write(chip,

			chip->usb_chgpth_base + ICL_BUF_CONFIG_REG,

			ICL_BUF_CFG_BIT, val);

	if (rc < 0) {

		dev_err(chip->dev,

			"Couldn't write 0x%02x to icl buf ctrl rc = %d\n",

			val, rc);

		return rc;

	}

	return 0;

}



static int configure_icl_control(struct smbchg_chip *chip, u8 val)

{

	if (!(chip->wa_flags & SMBCHG_ICL_CONTROL_WA))

		return 0;



	return smbchg_configure_icl_buffer(chip, val);

}



#define LOW_PWR_OPTIONS_REG	0xFF

#define FORCE_TLIM_BIT		BIT(4)

static int smbchg_force_tlim_en(struct smbchg_chip *chip, bool enable)
@@ -3651,6 +3685,12 @@ static int smbchg_otg_regulator_enable(struct regulator_dev *rdev) 


	chip->otg_retries = 0;

	chip->chg_otg_enabled = true;

	rc = configure_icl_control(chip, ICL_BUF_SS_DONE_VAL);

	if (rc) {

		dev_err(chip->dev, "Couldn't switch to soft start completion, rc=%d\n",

			rc);

		return rc;

	}

	smbchg_icl_loop_disable_check(chip);

	smbchg_otg_pulse_skip_disable(chip, REASON_OTG_ENABLED, true);
@@ -3686,6 +3726,12 @@ static int smbchg_otg_regulator_disable(struct regulator_dev *rdev) 
	chip->chg_otg_enabled = false;

	smbchg_otg_pulse_skip_disable(chip, REASON_OTG_ENABLED, false);

	smbchg_icl_loop_disable_check(chip);

	rc = configure_icl_control(chip, ICL_BUF_SYSON_LDO_VAL);

	if (rc) {

		dev_err(chip->dev, "Couldn't switch to Syson LDO, rc=%d\n",

			rc);

		rc = 0;

	}

	pr_smb(PR_STATUS, "Disabling OTG Boost\n");

	return rc;

}
@@ -7037,6 +7083,10 @@ static int smbchg_hw_init(struct smbchg_chip *chip) 
		pr_err("Couldn't write to MISC_TRIM_OPTIONS_15_8 rc=%d\n",

			rc);



	rc = configure_icl_control(chip, ICL_BUF_SYSON_LDO_VAL);

	if (rc)

		dev_err(chip->dev, "Couldn't switch to Syson LDO, rc=%d\n",

			rc);

	return rc;

}
@@ -7712,7 +7762,8 @@ static int smbchg_check_chg_version(struct smbchg_chip *chip) 
		chip->wa_flags |= SMBCHG_AICL_DEGLITCH_WA

				| SMBCHG_BATT_OV_WA

				| SMBCHG_CC_ESR_WA

				| SMBCHG_RESTART_WA;

				| SMBCHG_RESTART_WA

				| SMBCHG_ICL_CONTROL_WA;

		use_pmi8994_tables(chip);

		chip->schg_version = QPNP_SCHG;

		break;