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Commit 778e2ac5 authored by Ralf Baechle's avatar Ralf Baechle
Browse files

[MIPS] Fix build error on processors that don's support copy-on-write.

parent 4debe4f9
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+1 −1
Original line number Diff line number Diff line
@@ -63,7 +63,7 @@ void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen)
		return ioport_map(start, len);
	if (flags & IORESOURCE_MEM) {
		if (flags & IORESOURCE_CACHEABLE)
			return ioremap_cacheable_cow(start, len);
			return ioremap_cachable(start, len);
		return ioremap_nocache(start, len);
	}

+18 −0
Original line number Diff line number Diff line
@@ -282,6 +282,24 @@ static inline void __iomem * __ioremap_mode(phys_t offset, unsigned long size,
#define ioremap_nocache(offset, size)					\
	__ioremap_mode((offset), (size), _CACHE_UNCACHED)

/*
 * ioremap_cachable -   map bus memory into CPU space
 * @offset:         bus address of the memory
 * @size:           size of the resource to map
 *
 * ioremap_nocache performs a platform specific sequence of operations to
 * make bus memory CPU accessible via the readb/readw/readl/writeb/
 * writew/writel functions and the other mmio helpers. The returned
 * address is not guaranteed to be usable directly as a virtual
 * address.
 *
 * This version of ioremap ensures that the memory is marked cachable by
 * the CPU.  Also enables full write-combining.  Useful for some
 * memory-like regions on I/O busses.
 */
#define ioremap_cachable(offset, size)					\
	__ioremap_mode((offset), (size), PAGE_CACHABLE_DEFAULT)

/*
 * These two are MIPS specific ioremap variant.  ioremap_cacheable_cow
 * requests a cachable mapping, ioremap_uncached_accelerated requests a