Merge "ARM: dts: msm: Re-route SEC_I2S pins on MDM9650 TTP" (76f6e5e9) · Commits · e / devices / android_kernel_xiaomi_markw

arch/arm/boot/dts/qcom/mdm9650-pinctrl.dtsi

+141 −0

Original line number	Diff line number	Diff line
		@@ -1065,6 +1065,147 @@
		};
		};

		pmx_sec_mi2s_b_aux {
		sec_ws_b_sleep: sec_ws_b_sleep {
		mux {
		pins = "gpio20";
		function = "gpio";
		};

		config {
		pins = "gpio20";
		drive-strength = <2>; /* 2 mA */
		bias-pull-down; /* PULL DOWN */
		input-enable;
		};
		};

		sec_sck_b_sleep: sec_sck_b_sleep {
		mux {
		pins = "gpio23";
		function = "gpio";
		};

		config {
		pins = "gpio23";
		drive-strength = <2>; /* 2 mA */
		bias-pull-down; /* PULL DOWN */
		input-enable;
		};
		};

		sec_dout_b_sleep: sec_dout_b_sleep {
		mux {
		pins = "gpio22";
		function = "gpio";
		};

		config {
		pins = "gpio22";
		drive-strength = <2>; /* 2 mA */
		bias-pull-down; /* PULL DOWN */
		input-enable;
		};
		};

		sec_ws_b_active_master: sec_ws_b_active_master {
		mux {
		pins = "gpio20";
		function = "sec_mi2s_ws_b";
		};

		config {
		pins = "gpio20";
		drive-strength = <8>; /* 8 mA */
		bias-disable; /* NO PULL*/
		output-high;
		};
		};

		sec_sck_b_active_master: sec_sck_b_active_master {
		mux {
		pins = "gpio23";
		function = "sec_mi2s_sck_b";
		};

		config {
		pins = "gpio23";
		drive-strength = <8>; /* 8 mA */
		bias-disable; /* NO PULL*/
		output-high;
		};
		};

		sec_ws_b_active_slave: sec_ws_b_active_slave {
		mux {
		pins = "gpio20";
		function = "sec_mi2s_ws_b";
		};

		config {
		pins = "gpio20";
		drive-strength = <8>; /* 8 mA */
		bias-disable; /* NO PULL*/
		};
		};

		sec_sck_b_active_slave: sec_sck_b_active_slave {
		mux {
		pins = "gpio23";
		function = "sec_mi2s_sck_b";
		};

		config {
		pins = "gpio23";
		drive-strength = <8>; /* 8 mA */
		bias-disable; /* NO PULL*/
		};
		};

		sec_dout_b_active: sec_dout_b_active {
		mux {
		pins = "gpio22";
		function = "sec_mi2s_data1_b";
		};

		config {
		pins = "gpio22";
		drive-strength = <8>; /* 8 mA */
		bias-disable; /* NO PULL*/
		output-high;
		};
		};
		};

		pmx_sec_mi2s_b_aux_din {
		sec_din_b_sleep: sec_din_b_sleep {
		mux {
		pins = "gpio21";
		function = "gpio";
		};

		config {
		pins = "gpio21";
		drive-strength = <2>; /* 2 mA */
		bias-pull-down; /* PULL DOWN */
		input-enable;
		};
		};

		sec_din_b_active: sec_din_b_active {
		mux {
		pins = "gpio21";
		function = "sec_mi2s_data0_b";
		};

		config {
		pins = "gpio21";
		drive-strength = <8>; /* 8 mA */
		bias-disable; /* NO PULL */
		};
		};
		};

		sdc1_clk_on: sdc1_clk_on {
		config {
		pins = "sdc1_clk";

arch/arm/boot/dts/qcom/mdm9650-ttp.dts

+27 −0

Original line number	Diff line number	Diff line
		@@ -82,3 +82,30 @@
		&blsp1_uart2_hs {
		status = "disabled";
		};
		&sec_master {
		compatible = "qcom,wcd-gpio-ctrl";
		pinctrl-names = "aud_active", "aud_sleep";
		pinctrl-0 = <&sec_ws_b_active_master
		&sec_sck_b_active_master
		&sec_dout_b_active
		&sec_din_b_active>;
		pinctrl-1 = <&sec_ws_b_sleep
		&sec_sck_b_sleep
		&sec_dout_b_sleep
		&sec_din_b_sleep>;
		qcom,mi2s-auxpcm-cdc-gpios;
		};

		&sec_slave {
		compatible = "qcom,wcd-gpio-ctrl";
		pinctrl-names = "aud_active", "aud_sleep";
		pinctrl-0 = <&sec_ws_b_active_slave
		&sec_sck_b_active_slave
		&sec_dout_b_active
		&sec_din_b_active>;
		pinctrl-1 = <&sec_ws_b_sleep
		&sec_sck_b_sleep
		&sec_dout_b_sleep
		&sec_din_b_sleep>;
		qcom,mi2s-auxpcm-cdc-gpios;
		};