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Commit 76f14d0a authored by Maxime Ripard's avatar Maxime Ripard
Browse files

ARM: sunxi: dt: Add A10 UARTs to the dtsi. 



The Allwinner A10 SoC has 8 available UARTs, which is 6 more than on the
A13, so add the missing UARTs to the sun4i-a10 dtsi.

Signed-off-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: default avatarEmilio López <emilio@elopez.com.ar>
parent c08f4252

arch/arm/boot/dts/sun4i-a10.dtsi

+50 −0
Original line number Diff line number Diff line
@@ -57,5 +57,55 @@ 
			clocks = <&osc>;

			status = "disabled";

		};



		uart2: serial@01c28800 {

			compatible = "snps,dw-apb-uart";

			reg = <0x01c28800 0x400>;

			interrupts = <3>;

			reg-shift = <2>;

			reg-io-width = <4>;

			clocks = <&osc>;

			status = "disabled";

		};



		uart4: serial@01c29000 {

			compatible = "snps,dw-apb-uart";

			reg = <0x01c29000 0x400>;

			interrupts = <17>;

			reg-shift = <2>;

			reg-io-width = <4>;

			clocks = <&osc>;

			status = "disabled";

		};



		uart5: serial@01c29400 {

			compatible = "snps,dw-apb-uart";

			reg = <0x01c29400 0x400>;

			interrupts = <18>;

			reg-shift = <2>;

			reg-io-width = <4>;

			clocks = <&osc>;

			status = "disabled";

		};



		uart6: serial@01c29800 {

			compatible = "snps,dw-apb-uart";

			reg = <0x01c29800 0x400>;

			interrupts = <19>;

			reg-shift = <2>;

			reg-io-width = <4>;

			clocks = <&osc>;

			status = "disabled";

		};



		uart7: serial@01c29c00 {

			compatible = "snps,dw-apb-uart";

			reg = <0x01c29c00 0x400>;

			interrupts = <20>;

			reg-shift = <2>;

			reg-io-width = <4>;

			clocks = <&osc>;

			status = "disabled";

		};

	};

};