Commit 7605b390 authored Mar 20, 2007 by Ralf Baechle

[MIPS] Fix pipeline hazard.



In the the sequence:
        ei
        ..
        mfc0    $x, $status

the mfc0 may not see the SR_IE bit set. This was a deliberate bug in the
kernel code because we knew this was a safe thing to do on all R2 silicon
so far but new silicon is changing this.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

parent 83598f1c

include/asm-mips/hazards.h

+1 −0

Original line number	Diff line number	Diff line
		@@ -52,6 +52,7 @@ ASMMACRO(tlb_probe_hazard,
		_ehb
		)
		ASMMACRO(irq_enable_hazard,
		_ehb
		)
		ASMMACRO(irq_disable_hazard,
		_ehb