arm64: kernel: add support for cpu cache information

This patch adds support for cacheinfo on ARM64.

On ARMv8, the cache hierarchy can be identified through Cache Level ID
(CLIDR) register while the cache geometry is provided by Cache Size ID
(CCSIDR) register.

Since the architecture doesn't provide any way of detecting the cpus
sharing particular cache, device tree is used for the same purpose.

Change-Id: I5bce360260312676b06c9129d78b8547c27e6609
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Git-commit: 5d425c18653731af62831d30a4fa023d532657a9
Git-repo: https://source.codeaurora.org/quic/la/kernel/msm-4.9


[tengfei@codeaurora.org: resolve trivial merge conflicts]
Signed-off-by: Teng Fei Fan <tengfei@codeaurora.org>