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Commit 7346bfa0 authored by Paulo Zanoni's avatar Paulo Zanoni Committed by Daniel Vetter
Browse files

drm/i915: use TU_SIZE macro at intel_dp_set_m_n 



Much simpler and looks more like the M/N code inside intel_display.c.

Signed-off-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent d6c0d722

drivers/gpu/drm/i915/intel_dp.c

+2 −5
Original line number Diff line number Diff line
@@ -794,9 +794,7 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode, 
			     mode->clock, adjusted_mode->clock, &m_n);



	if (HAS_PCH_SPLIT(dev)) {

		I915_WRITE(TRANSDATA_M1(pipe),

			   ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |

			   m_n.gmch_m);

		I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);

		I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);

		I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);

		I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
@@ -807,8 +805,7 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode, 
		I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);

	} else {

		I915_WRITE(PIPE_GMCH_DATA_M(pipe),

			   ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |

			   m_n.gmch_m);

			   TU_SIZE(m_n.tu) | m_n.gmch_m);

		I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);

		I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);

		I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);