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Commit 7338a065 authored by Greg Kroah-Hartman's avatar Greg Kroah-Hartman
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Merge tag 'usb-for-v3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb into usb-next 



Felipe writes:

usb: patches for v3.15

another substantial pull request with new features all over
the place.

dwc3 got a bit closer towards hibernation support with after
a few patches re-factoring code to be reused for hibernation.
Also in dwc3 two new workarounds for known silicon bugs have
been implemented, some randconfig build errors have been fixed,
and it was taught about the new generic phy layer.

MUSB on AM335x now supports isochronous transfers thanks to
George Cherian's work.

The atmel_usba driver got two crash fixes: one when no endpoint
was specified in DeviceTree data and another when stopping the UDC
in DEBUG builds.

Function FS got a much needed fix to ffs_epfile_io() which was
copying too much data to userspace in some cases.

The printer gadget got a fix for a possible deadlock and plugged
a memory leak.

Ethernet drivers now use NAPI for RX which gives improved throughput.

Other than that, the usual miscelaneous fixes, cleanups, and
the like.

Signed-of-by: default avatarFelipe Balbi <balbi@ti.com>
parents c9050b64 4b76e14d

Documentation/devicetree/bindings/usb/usb-phy.txt→Documentation/devicetree/bindings/phy/ti-phy.txt

+86 −0
Original line number Diff line number Diff line 
USB PHY

TI PHY: DT DOCUMENTATION FOR PHYs in TI PLATFORMs



OMAP CONTROL PHY



Required properties:

 - compatible: Should be one of

 "ti,control-phy-otghs" - if it has otghs_control mailbox register as on OMAP4.

 "ti,control-phy-usb2" - if it has Power down bit in control_dev_conf register

                        e.g. USB2_PHY on OMAP5.

 "ti,control-phy-pipe3" - if it has DPLL and individual Rx & Tx power control

                        e.g. USB3 PHY and SATA PHY on OMAP5.

 "ti,control-phy-usb2-dra7" - if it has power down register like USB2 PHY on

                        DRA7 platform.

 "ti,control-phy-usb2-am437" - if it has power down register like USB2 PHY on

                        AM437 platform.

 - reg : Address and length of the register set for the device. It contains

   the address of "otghs_control" for control-phy-otghs or "power" register

   for other types.

 - reg-names: should be "otghs_control" control-phy-otghs and "power" for

   other types.



omap_control_usb: omap-control-usb@4a002300 {

        compatible = "ti,control-phy-otghs";

        reg = <0x4a00233c 0x4>;

        reg-names = "otghs_control";

};



OMAP USB2 PHY
@@ -21,15 +46,22 @@ usb2phy@4a0ad080 { 
	#phy-cells = <0>;

};



OMAP USB3 PHY

TI PIPE3 PHY



Required properties:

 - compatible: Should be "ti,omap-usb3"

 - compatible: Should be "ti,phy-usb3" or "ti,phy-pipe3-sata".

   "ti,omap-usb3" is deprecated.

 - reg : Address and length of the register set for the device.

 - reg-names: The names of the register addresses corresponding to the registers

   filled in "reg".

 - #phy-cells: determine the number of cells that should be given in the

   phandle while referencing this phy.

 - clocks: a list of phandles and clock-specifier pairs, one for each entry in

   clock-names.

 - clock-names: should include:

   * "wkupclk" - wakeup clock.

   * "sysclk" - system clock.

   * "refclk" - reference clock.



Optional properties:

 - ctrl-module : phandle of the control module used by PHY driver to power on
@@ -38,11 +70,17 @@ Optional properties: 
This is usually a subnode of ocp2scp to which it is connected.



usb3phy@4a084400 {

	compatible = "ti,omap-usb3";

	compatible = "ti,phy-usb3";

	reg = <0x4a084400 0x80>,

	      <0x4a084800 0x64>,

	      <0x4a084c00 0x40>;

	reg-names = "phy_rx", "phy_tx", "pll_ctrl";

	ctrl-module = <&omap_control_usb>;

	#phy-cells = <0>;

	clocks = <&usb_phy_cm_clk32k>,

		 <&sys_clkin>,

		 <&usb_otg_ss_refclk960m>;

	clock-names =	"wkupclk",

			"sysclk",

			"refclk";

};

Documentation/devicetree/bindings/usb/dwc3.txt

+4 −2
Original line number Diff line number Diff line
@@ -6,11 +6,13 @@ Required properties: 
 - compatible: must be "snps,dwc3"

 - reg : Address and length of the register set for the device

 - interrupts: Interrupts used by the dwc3 controller.



Optional properties:

 - usb-phy : array of phandle for the PHY device.  The first element

   in the array is expected to be a handle to the USB2/HS PHY and

   the second element is expected to be a handle to the USB3/SS PHY



Optional properties:

 - phys: from the *Generic PHY* bindings

 - phy-names: from the *Generic PHY* bindings

 - tx-fifo-resize: determines if the FIFO *has* to be reallocated.



This is usually a subnode to DWC3 glue to which it is connected.

Documentation/devicetree/bindings/usb/mxs-phy.txt

+7 −1
Original line number Diff line number Diff line 
* Freescale MXS USB Phy Device



Required properties:

- compatible: Should be "fsl,imx23-usbphy"

- compatible: should contain:

	* "fsl,imx23-usbphy" for imx23 and imx28

	* "fsl,imx6q-usbphy" for imx6dq and imx6dl

	* "fsl,imx6sl-usbphy" for imx6sl

  "fsl,imx23-usbphy" is still a fallback for other strings

- reg: Should contain registers location and length

- interrupts: Should contain phy interrupt

- fsl,anatop: phandle for anatop register, it is only for imx6 SoC series



Example:

usbphy1: usbphy@020c9000 {

	compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";

	reg = <0x020c9000 0x1000>;

	interrupts = <0 44 0x04>;

	fsl,anatop = <&anatop>;

};

Documentation/devicetree/bindings/usb/omap-usb.txt

+0 −24
Original line number Diff line number Diff line
@@ -76,27 +76,3 @@ omap_dwc3 { 
	ranges;

};

OMAP CONTROL USB



Required properties:

 - compatible: Should be one of

 "ti,control-phy-otghs" - if it has otghs_control mailbox register as on OMAP4.

 "ti,control-phy-usb2" - if it has Power down bit in control_dev_conf register

			e.g. USB2_PHY on OMAP5.

 "ti,control-phy-pipe3" - if it has DPLL and individual Rx & Tx power control

			e.g. USB3 PHY and SATA PHY on OMAP5.

 "ti,control-phy-dra7usb2" - if it has power down register like USB2 PHY on

			DRA7 platform.

 "ti,control-phy-am437usb2" - if it has power down register like USB2 PHY on

			AM437 platform.

 - reg : Address and length of the register set for the device. It contains

   the address of "otghs_control" for control-phy-otghs or "power" register

   for other types.

 - reg-names: should be "otghs_control" control-phy-otghs and "power" for

   other types.



omap_control_usb: omap-control-usb@4a002300 {

	compatible = "ti,control-phy-otghs";

	reg = <0x4a00233c 0x4>;

	reg-names = "otghs_control";

};

drivers/usb/dwc3/core.c

+221 −30
Original line number Diff line number Diff line
@@ -61,9 +61,10 @@ void dwc3_set_mode(struct dwc3 *dwc, u32 mode) 
 * dwc3_core_soft_reset - Issues core soft reset and PHY reset

 * @dwc: pointer to our context structure

 */

static void dwc3_core_soft_reset(struct dwc3 *dwc)

static int dwc3_core_soft_reset(struct dwc3 *dwc)

{

	u32		reg;

	int		ret;



	/* Before Resetting PHY, put Core in Reset */

	reg = dwc3_readl(dwc->regs, DWC3_GCTL);
@@ -82,6 +83,15 @@ static void dwc3_core_soft_reset(struct dwc3 *dwc) 


	usb_phy_init(dwc->usb2_phy);

	usb_phy_init(dwc->usb3_phy);

	ret = phy_init(dwc->usb2_generic_phy);

	if (ret < 0)

		return ret;



	ret = phy_init(dwc->usb3_generic_phy);

	if (ret < 0) {

		phy_exit(dwc->usb2_generic_phy);

		return ret;

	}

	mdelay(100);



	/* Clear USB3 PHY reset */
@@ -100,6 +110,8 @@ static void dwc3_core_soft_reset(struct dwc3 *dwc) 
	reg = dwc3_readl(dwc->regs, DWC3_GCTL);

	reg &= ~DWC3_GCTL_CORESOFTRESET;

	dwc3_writel(dwc->regs, DWC3_GCTL, reg);



	return 0;

}



/**
@@ -242,6 +254,90 @@ static void dwc3_event_buffers_cleanup(struct dwc3 *dwc) 
	}

}



static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)

{

	if (!dwc->has_hibernation)

		return 0;



	if (!dwc->nr_scratch)

		return 0;



	dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,

			DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);

	if (!dwc->scratchbuf)

		return -ENOMEM;



	return 0;

}



static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)

{

	dma_addr_t scratch_addr;

	u32 param;

	int ret;



	if (!dwc->has_hibernation)

		return 0;



	if (!dwc->nr_scratch)

		return 0;



	 /* should never fall here */

	if (!WARN_ON(dwc->scratchbuf))

		return 0;



	scratch_addr = dma_map_single(dwc->dev, dwc->scratchbuf,

			dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,

			DMA_BIDIRECTIONAL);

	if (dma_mapping_error(dwc->dev, scratch_addr)) {

		dev_err(dwc->dev, "failed to map scratch buffer\n");

		ret = -EFAULT;

		goto err0;

	}



	dwc->scratch_addr = scratch_addr;



	param = lower_32_bits(scratch_addr);



	ret = dwc3_send_gadget_generic_command(dwc,

			DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);

	if (ret < 0)

		goto err1;



	param = upper_32_bits(scratch_addr);



	ret = dwc3_send_gadget_generic_command(dwc,

			DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);

	if (ret < 0)

		goto err1;



	return 0;



err1:

	dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch *

			DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);



err0:

	return ret;

}



static void dwc3_free_scratch_buffers(struct dwc3 *dwc)

{

	if (!dwc->has_hibernation)

		return;



	if (!dwc->nr_scratch)

		return;



	 /* should never fall here */

	if (!WARN_ON(dwc->scratchbuf))

		return;



	dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch *

			DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);

	kfree(dwc->scratchbuf);

}



static void dwc3_core_num_eps(struct dwc3 *dwc)

{

	struct dwc3_hwparams	*parms = &dwc->hwparams;
@@ -277,6 +373,7 @@ static void dwc3_cache_hwparams(struct dwc3 *dwc) 
static int dwc3_core_init(struct dwc3 *dwc)

{

	unsigned long		timeout;

	u32			hwparams4 = dwc->hwparams.hwparams4;

	u32			reg;

	int			ret;
@@ -306,7 +403,9 @@ static int dwc3_core_init(struct dwc3 *dwc) 
		cpu_relax();

	} while (true);



	dwc3_core_soft_reset(dwc);

	ret = dwc3_core_soft_reset(dwc);

	if (ret)

		goto err0;



	reg = dwc3_readl(dwc->regs, DWC3_GCTL);

	reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
@@ -314,8 +413,30 @@ static int dwc3_core_init(struct dwc3 *dwc) 


	switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {

	case DWC3_GHWPARAMS1_EN_PWROPT_CLK:

		/**

		 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an

		 * issue which would cause xHCI compliance tests to fail.

		 *

		 * Because of that we cannot enable clock gating on such

		 * configurations.

		 *

		 * Refers to:

		 *

		 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based

		 * SOF/ITP Mode Used

		 */

		if ((dwc->dr_mode == USB_DR_MODE_HOST ||

				dwc->dr_mode == USB_DR_MODE_OTG) &&

				(dwc->revision >= DWC3_REVISION_210A &&

				dwc->revision <= DWC3_REVISION_250A))

			reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;

		else

			reg &= ~DWC3_GCTL_DSBLCLKGTNG;

		break;

	case DWC3_GHWPARAMS1_EN_PWROPT_HIB:

		/* enable hibernation here */

		dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);

		break;

	default:

		dev_dbg(dwc->dev, "No power optimization available\n");

	}
@@ -333,16 +454,36 @@ static int dwc3_core_init(struct dwc3 *dwc) 


	dwc3_writel(dwc->regs, DWC3_GCTL, reg);



	ret = dwc3_alloc_scratch_buffers(dwc);

	if (ret)

		goto err1;



	ret = dwc3_setup_scratch_buffers(dwc);

	if (ret)

		goto err2;



	return 0;



err2:

	dwc3_free_scratch_buffers(dwc);



err1:

	usb_phy_shutdown(dwc->usb2_phy);

	usb_phy_shutdown(dwc->usb3_phy);

	phy_exit(dwc->usb2_generic_phy);

	phy_exit(dwc->usb3_generic_phy);



err0:

	return ret;

}



static void dwc3_core_exit(struct dwc3 *dwc)

{

	dwc3_free_scratch_buffers(dwc);

	usb_phy_shutdown(dwc->usb2_phy);

	usb_phy_shutdown(dwc->usb3_phy);

	phy_exit(dwc->usb2_generic_phy);

	phy_exit(dwc->usb3_generic_phy);

}



#define DWC3_ALIGN_MASK		(16 - 1)
@@ -411,32 +552,52 @@ static int dwc3_probe(struct platform_device *pdev) 


	if (IS_ERR(dwc->usb2_phy)) {

		ret = PTR_ERR(dwc->usb2_phy);



		/*

		 * if -ENXIO is returned, it means PHY layer wasn't

		 * enabled, so it makes no sense to return -EPROBE_DEFER

		 * in that case, since no PHY driver will ever probe.

		 */

		if (ret == -ENXIO)

		if (ret == -ENXIO || ret == -ENODEV) {

			dwc->usb2_phy = NULL;

		} else if (ret == -EPROBE_DEFER) {

			return ret;



		} else {

			dev_err(dev, "no usb2 phy configured\n");

		return -EPROBE_DEFER;

			return ret;

		}

	}



	if (IS_ERR(dwc->usb3_phy)) {

		ret = PTR_ERR(dwc->usb3_phy);

		if (ret == -ENXIO || ret == -ENODEV) {

			dwc->usb3_phy = NULL;

		} else if (ret == -EPROBE_DEFER) {

			return ret;

		} else {

			dev_err(dev, "no usb3 phy configured\n");

			return ret;

		}

	}



		/*

		 * if -ENXIO is returned, it means PHY layer wasn't

		 * enabled, so it makes no sense to return -EPROBE_DEFER

		 * in that case, since no PHY driver will ever probe.

		 */

		if (ret == -ENXIO)

	dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");

	if (IS_ERR(dwc->usb2_generic_phy)) {

		ret = PTR_ERR(dwc->usb2_generic_phy);

		if (ret == -ENOSYS || ret == -ENODEV) {

			dwc->usb2_generic_phy = NULL;

		} else if (ret == -EPROBE_DEFER) {

			return ret;

		} else {

			dev_err(dev, "no usb2 phy configured\n");

			return ret;

		}

	}



	dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");

	if (IS_ERR(dwc->usb3_generic_phy)) {

		ret = PTR_ERR(dwc->usb3_generic_phy);

		if (ret == -ENOSYS || ret == -ENODEV) {

			dwc->usb3_generic_phy = NULL;

		} else if (ret == -EPROBE_DEFER) {

			return ret;

		} else {

			dev_err(dev, "no usb3 phy configured\n");

		return -EPROBE_DEFER;

			return ret;

		}

	}



	dwc->xhci_resources[0].start = res->start;
@@ -479,6 +640,14 @@ static int dwc3_probe(struct platform_device *pdev) 
		goto err0;

	}



	if (IS_ENABLED(CONFIG_USB_DWC3_HOST))

		dwc->dr_mode = USB_DR_MODE_HOST;

	else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))

		dwc->dr_mode = USB_DR_MODE_PERIPHERAL;



	if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)

		dwc->dr_mode = USB_DR_MODE_OTG;



	ret = dwc3_core_init(dwc);

	if (ret) {

		dev_err(dev, "failed to initialize core\n");
@@ -487,21 +656,20 @@ static int dwc3_probe(struct platform_device *pdev) 


	usb_phy_set_suspend(dwc->usb2_phy, 0);

	usb_phy_set_suspend(dwc->usb3_phy, 0);

	ret = phy_power_on(dwc->usb2_generic_phy);

	if (ret < 0)

		goto err1;



	ret = phy_power_on(dwc->usb3_generic_phy);

	if (ret < 0)

		goto err_usb2phy_power;



	ret = dwc3_event_buffers_setup(dwc);

	if (ret) {

		dev_err(dwc->dev, "failed to setup event buffers\n");

		goto err1;

		goto err_usb3phy_power;

	}



	if (IS_ENABLED(CONFIG_USB_DWC3_HOST))

		dwc->dr_mode = USB_DR_MODE_HOST;

	else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))

		dwc->dr_mode = USB_DR_MODE_PERIPHERAL;



	if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)

		dwc->dr_mode = USB_DR_MODE_OTG;



	switch (dwc->dr_mode) {

	case USB_DR_MODE_PERIPHERAL:

		dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
@@ -568,6 +736,12 @@ err3: 
err2:

	dwc3_event_buffers_cleanup(dwc);



err_usb3phy_power:

	phy_power_off(dwc->usb3_generic_phy);



err_usb2phy_power:

	phy_power_off(dwc->usb2_generic_phy);



err1:

	usb_phy_set_suspend(dwc->usb2_phy, 1);

	usb_phy_set_suspend(dwc->usb3_phy, 1);
@@ -585,6 +759,8 @@ static int dwc3_remove(struct platform_device *pdev) 


	usb_phy_set_suspend(dwc->usb2_phy, 1);

	usb_phy_set_suspend(dwc->usb3_phy, 1);

	phy_power_off(dwc->usb2_generic_phy);

	phy_power_off(dwc->usb3_generic_phy);



	pm_runtime_put_sync(&pdev->dev);

	pm_runtime_disable(&pdev->dev);
@@ -682,6 +858,8 @@ static int dwc3_suspend(struct device *dev) 


	usb_phy_shutdown(dwc->usb3_phy);

	usb_phy_shutdown(dwc->usb2_phy);

	phy_exit(dwc->usb2_generic_phy);

	phy_exit(dwc->usb3_generic_phy);



	return 0;

}
@@ -690,9 +868,17 @@ static int dwc3_resume(struct device *dev) 
{

	struct dwc3	*dwc = dev_get_drvdata(dev);

	unsigned long	flags;

	int		ret;



	usb_phy_init(dwc->usb3_phy);

	usb_phy_init(dwc->usb2_phy);

	ret = phy_init(dwc->usb2_generic_phy);

	if (ret < 0)

		return ret;



	ret = phy_init(dwc->usb3_generic_phy);

	if (ret < 0)

		goto err_usb2phy_init;



	spin_lock_irqsave(&dwc->lock, flags);
@@ -716,6 +902,11 @@ static int dwc3_resume(struct device *dev) 
	pm_runtime_enable(dev);



	return 0;



err_usb2phy_init:

	phy_exit(dwc->usb2_generic_phy);



	return ret;

}



static const struct dev_pm_ops dwc3_dev_pm_ops = {