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Commit 7255f87a authored by Alexander Shiyan's avatar Alexander Shiyan Committed by Arnd Bergmann
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ARM: clps711x: Fix lowlevel debug-macro



CTS signal can not be used for the port and tied to any logic state.
In this case we have an infinite loop waiting for the signal. For fix
this problem, checking CTS removed, waiting for the signal "busy" was
postponed after the byte write to the port.

Signed-off-by: default avatarAlexander Shiyan <shc_work@mail.ru>
parent 61ae48c3
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+1 −7
Original line number Diff line number Diff line
@@ -28,17 +28,11 @@
		.endm

		.macro	waituart,rd,rx
1001:		ldr	\rd, [\rx, #0x0140]	@ SYSFLGx
		tst	\rd, #1 << 11		@ UBUSYx
		bne	1001b
		.endm

		.macro	busyuart,rd,rx
		tst	\rx, #0x1000		@ UART2 does not have CTS here
		bne	1002f
1001:		ldr	\rd, [\rx, #0x0140]	@ SYSFLGx
		tst	\rd, #1 << 8		@ CTS
		tst	\rd, #1 << 11		@ UBUSYx
		bne	1001b
1002:
		.endm