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Commit 71fc5099 authored by Magnus Damm's avatar Magnus Damm Committed by Paul Mundt
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ARM: mach-shmobile: sh73a0 CPGA fix for PLL CFG bit 



PLL1 and PLL2 in the sh73a0 CPGA has a CFG bit that
must be taken into account to correctly calculate the
frequency.

Signed-off-by: default avatarMagnus Damm <damm@opensource.se>
Signed-off-by: default avatarPaul Mundt <lethal@linux-sh.org>
parent 2150dace

arch/arm/mach-shmobile/clock-sh73a0.c

+9 −1
Original line number Diff line number Diff line
@@ -118,8 +118,16 @@ static unsigned long pll_recalc(struct clk *clk) 
{

	unsigned long mult = 1;



	if (__raw_readl(PLLECR) & (1 << clk->enable_bit))

	if (__raw_readl(PLLECR) & (1 << clk->enable_bit)) {

		mult = (((__raw_readl(clk->enable_reg) >> 24) & 0x3f) + 1);

		/* handle CFG bit for PLL1 and PLL2 */

		switch (clk->enable_bit) {

		case 1:

		case 2:

			if (__raw_readl(clk->enable_reg) & (1 << 20))

				mult *= 2;

		}

	}



	return clk->parent->rate * mult;

}