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Commit 71e18497 authored by Michael Neuling's avatar Michael Neuling Committed by Benjamin Herrenschmidt
Browse files

powerpc: POWER8 cputable entry 



Signed-off-by: default avatarMichael Neuling <mikey@neuling.org>
Signed-off-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
parent aec937b1

arch/powerpc/include/asm/cputable.h

+10 −2
Original line number Diff line number Diff line
@@ -401,6 +401,14 @@ extern const char *powerpc_base_platform; 
	    CPU_FTR_DSCR | CPU_FTR_SAO  | CPU_FTR_ASYM_SMT | \

	    CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \

	    CPU_FTR_ICSWX | CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY)

#define CPU_FTRS_POWER8 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \

	    CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\

	    CPU_FTR_MMCRA | CPU_FTR_SMT | \

	    CPU_FTR_COHERENT_ICACHE | \

	    CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \

	    CPU_FTR_DSCR | CPU_FTR_SAO  | \

	    CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \

	    CPU_FTR_ICSWX | CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY)

#define CPU_FTRS_CELL	(CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \

	    CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \

	    CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
@@ -421,8 +429,8 @@ extern const char *powerpc_base_platform; 
#define CPU_FTRS_POSSIBLE	\

	    (CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 |	\

	    CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_POWER6 |	\

	    CPU_FTRS_POWER7 | CPU_FTRS_CELL | CPU_FTRS_PA6T |		\

	    CPU_FTR_VSX)

	    CPU_FTRS_POWER7 | CPU_FTRS_POWER8 | CPU_FTRS_CELL |		\

	    CPU_FTRS_PA6T | CPU_FTR_VSX)

#endif

#else

enum {

arch/powerpc/include/asm/mmu.h

+1 −0
Original line number Diff line number Diff line
@@ -101,6 +101,7 @@ 
#define MMU_FTRS_POWER5		MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE

#define MMU_FTRS_POWER6		MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE

#define MMU_FTRS_POWER7		MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE

#define MMU_FTRS_POWER8		MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE

#define MMU_FTRS_CELL		MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \

				MMU_FTR_CI_LARGE_PAGE

#define MMU_FTRS_PA6T		MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \

arch/powerpc/include/asm/reg.h

+1 −0
Original line number Diff line number Diff line
@@ -1029,6 +1029,7 @@ 
#define PVR_970MP	0x0044

#define PVR_970GX	0x0045

#define PVR_POWER7p	0x004A

#define PVR_POWER8	0x004B

#define PVR_BE		0x0070

#define PVR_PA6T	0x0090

arch/powerpc/kernel/cputable.c

+21 −0
Original line number Diff line number Diff line
@@ -96,6 +96,10 @@ extern void __restore_cpu_e5500(void); 
				 PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP | \

				 PPC_FEATURE_TRUE_LE | \

				 PPC_FEATURE_PSERIES_PERFMON_COMPAT)

#define COMMON_USER_POWER8	(COMMON_USER_PPC64 | PPC_FEATURE_ARCH_2_06 |\

				 PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP | \

				 PPC_FEATURE_TRUE_LE | \

				 PPC_FEATURE_PSERIES_PERFMON_COMPAT)

#define COMMON_USER_PA6T	(COMMON_USER_PPC64 | PPC_FEATURE_PA6T |\

				 PPC_FEATURE_TRUE_LE | \

				 PPC_FEATURE_HAS_ALTIVEC_COMP)
@@ -465,6 +469,23 @@ static struct cpu_spec __initdata cpu_specs[] = { 
		.cpu_restore		= __restore_cpu_power7,

		.platform		= "power7+",

	},

	{	/* Power8 */

		.pvr_mask		= 0xffff0000,

		.pvr_value		= 0x004b0000,

		.cpu_name		= "POWER8 (raw)",

		.cpu_features		= CPU_FTRS_POWER8,

		.cpu_user_features	= COMMON_USER_POWER8,

		.mmu_features		= MMU_FTRS_POWER8,

		.icache_bsize		= 128,

		.dcache_bsize		= 128,

		.num_pmcs		= 6,

		.pmc_type		= PPC_PMC_IBM,

		.oprofile_cpu_type	= "ppc64/power8",

		.oprofile_type		= PPC_OPROFILE_POWER4,

		.cpu_setup		= __setup_cpu_power8,

		.cpu_restore		= __restore_cpu_power8,

		.platform		= "power8",

	},

	{	/* Cell Broadband Engine */

		.pvr_mask		= 0xffff0000,

		.pvr_value		= 0x00700000,