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Commit 71b70ee9 authored by Loc Ho's avatar Loc Ho Committed by Tejun Heo
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arm64: Add APM X-Gene SoC 15Gbps Multi-purpose PHY DTS entries 



This patch adds the DTS entries for the APM X-Gene SoC 15Gbps Multi-purpose
PHY driver. The PHY for SATA controller 2 and 3 are enabled by default.

Signed-off-by: default avatarLoc Ho <lho@apm.com>
Signed-off-by: default avatarTuan Phan <tphan@apm.com>
Signed-off-by: default avatarSuman Tripathi <stripathi@apm.com>
Acked-by: default avatarArnd Bergmann <arnd@arndb.de>
Signed-off-by: default avatarTejun Heo <tj@kernel.org>
parent cdf457a4

arch/arm64/boot/dts/apm-storm.dtsi

+72 −0
Original line number Diff line number Diff line
@@ -176,6 +176,48 @@ 
				reg-names = "csr-reg";

				clock-output-names = "eth8clk";

			};



			sataphy1clk: sataphy1clk@1f21c000 {

				compatible = "apm,xgene-device-clock";

				#clock-cells = <1>;

				clocks = <&socplldiv2 0>;

				reg = <0x0 0x1f21c000 0x0 0x1000>;

				reg-names = "csr-reg";

				clock-output-names = "sataphy1clk";

				status = "disabled";

				csr-offset = <0x4>;

				csr-mask = <0x00>;

				enable-offset = <0x0>;

				enable-mask = <0x06>;

			};



			sataphy2clk: sataphy1clk@1f22c000 {

				compatible = "apm,xgene-device-clock";

				#clock-cells = <1>;

				clocks = <&socplldiv2 0>;

				reg = <0x0 0x1f22c000 0x0 0x1000>;

				reg-names = "csr-reg";

				clock-output-names = "sataphy2clk";

				status = "ok";

				csr-offset = <0x4>;

				csr-mask = <0x3a>;

				enable-offset = <0x0>;

				enable-mask = <0x06>;

			};



			sataphy3clk: sataphy1clk@1f23c000 {

				compatible = "apm,xgene-device-clock";

				#clock-cells = <1>;

				clocks = <&socplldiv2 0>;

				reg = <0x0 0x1f23c000 0x0 0x1000>;

				reg-names = "csr-reg";

				clock-output-names = "sataphy3clk";

				status = "ok";

				csr-offset = <0x4>;

				csr-mask = <0x3a>;

				enable-offset = <0x0>;

				enable-mask = <0x06>;

			};

		};



		serial0: serial@1c020000 {
@@ -187,5 +229,35 @@ 
			interrupt-parent = <&gic>;

			interrupts = <0x0 0x4c 0x4>;

		};



		phy1: phy@1f21a000 {

			compatible = "apm,xgene-phy";

			reg = <0x0 0x1f21a000 0x0 0x100>;

			#phy-cells = <1>;

			clocks = <&sataphy1clk 0>;

			status = "disabled";

			apm,tx-boost-gain = <30 30 30 30 30 30>;

			apm,tx-eye-tuning = <2 10 10 2 10 10>;

		};



		phy2: phy@1f22a000 {

			compatible = "apm,xgene-phy";

			reg = <0x0 0x1f22a000 0x0 0x100>;

			#phy-cells = <1>;

			clocks = <&sataphy2clk 0>;

			status = "ok";

			apm,tx-boost-gain = <30 30 30 30 30 30>;

			apm,tx-eye-tuning = <1 10 10 2 10 10>;

		};



		phy3: phy@1f23a000 {

			compatible = "apm,xgene-phy";

			reg = <0x0 0x1f23a000 0x0 0x100>;

			#phy-cells = <1>;

			clocks = <&sataphy3clk 0>;

			status = "ok";

			apm,tx-boost-gain = <31 31 31 31 31 31>;

			apm,tx-eye-tuning = <2 10 10 2 10 10>;

		};

	};

};