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Commit 7115e3fc authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'perf-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

* 'perf-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (121 commits)
  perf symbols: Increase symbol KSYM_NAME_LEN size
  perf hists browser: Refuse 'a' hotkey on non symbolic views
  perf ui browser: Use libslang to read keys
  perf tools: Fix tracing info recording
  perf hists browser: Elide DSO column when it is set to just one DSO, ditto for threads
  perf hists: Don't consider filtered entries when calculating column widths
  perf hists: Don't decay total_period for filtered entries
  perf hists browser: Honour symbol_conf.show_{nr_samples,total_period}
  perf hists browser: Do not exit on tab key with single event
  perf annotate browser: Don't change selection line when returning from callq
  perf tools: handle endianness of feature bitmap
  perf tools: Add prelink suggestion to dso update message
  perf script: Fix unknown feature comment
  perf hists browser: Apply the dso and thread filters when merging new batches
  perf hists: Move the dso and thread filters from hist_browser
  perf ui browser: Honour the xterm colors
  perf top tui: Give color hints just on the percentage, like on --stdio
  perf ui browser: Make the colors configurable and change the defaults
  perf tui: Remove unneeded call to newtCls on startup
  perf hists: Don't format the percentage on hist_entry__snprintf
  ...

Fix up conflicts in arch/x86/kernel/kprobes.c manually.

Ingo's tree did the insane "add volatile to const array", which just
doesn't make sense ("volatile const"?).  But we could remove the const
*and* make the array volatile to make doubly sure that gcc doesn't
optimize it away..

Also fix up kernel/trace/ring_buffer.c non-data-conflicts manually: the
reader_lock has been turned into a raw lock by the core locking merge,
and there was a new user of it introduced in this perf core merge.  Make
sure that new use also uses the raw accessor functions.
parents 1f6e0517 c752d040

arch/m32r/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -10,6 +10,7 @@ config M32R 
	select HAVE_GENERIC_HARDIRQS

	select GENERIC_IRQ_PROBE

	select GENERIC_IRQ_SHOW

	select GENERIC_ATOMIC64



config SBUS

	bool

arch/x86/include/asm/nmi.h

+18 −19
Original line number Diff line number Diff line
@@ -22,27 +22,26 @@ void arch_trigger_all_cpu_backtrace(void); 
#define arch_trigger_all_cpu_backtrace arch_trigger_all_cpu_backtrace

#endif



/*

 * Define some priorities for the nmi notifier call chain.

 *

 * Create a local nmi bit that has a higher priority than

 * external nmis, because the local ones are more frequent.

 *

 * Also setup some default high/normal/low settings for

 * subsystems to registers with.  Using 4 bits to separate

 * the priorities.  This can go a lot higher if needed be.

 */



#define NMI_LOCAL_SHIFT		16	/* randomly picked */

#define NMI_LOCAL_BIT		(1ULL << NMI_LOCAL_SHIFT)

#define NMI_HIGH_PRIOR		(1ULL << 8)

#define NMI_NORMAL_PRIOR	(1ULL << 4)

#define NMI_LOW_PRIOR		(1ULL << 0)

#define NMI_LOCAL_HIGH_PRIOR	(NMI_LOCAL_BIT | NMI_HIGH_PRIOR)

#define NMI_LOCAL_NORMAL_PRIOR	(NMI_LOCAL_BIT | NMI_NORMAL_PRIOR)

#define NMI_LOCAL_LOW_PRIOR	(NMI_LOCAL_BIT | NMI_LOW_PRIOR)

#define NMI_FLAG_FIRST	1



enum {

	NMI_LOCAL=0,

	NMI_UNKNOWN,

	NMI_MAX

};



#define NMI_DONE	0

#define NMI_HANDLED	1



typedef int (*nmi_handler_t)(unsigned int, struct pt_regs *);



int register_nmi_handler(unsigned int, nmi_handler_t, unsigned long,

			 const char *);



void unregister_nmi_handler(unsigned int, const char *);



void stop_nmi(void);

void restart_nmi(void);

void local_touch_nmi(void);



#endif /* _ASM_X86_NMI_H */

arch/x86/include/asm/perf_event.h

+52 −3
Original line number Diff line number Diff line
@@ -29,6 +29,9 @@ 
#define ARCH_PERFMON_EVENTSEL_INV			(1ULL << 23)

#define ARCH_PERFMON_EVENTSEL_CMASK			0xFF000000ULL



#define AMD_PERFMON_EVENTSEL_GUESTONLY			(1ULL << 40)

#define AMD_PERFMON_EVENTSEL_HOSTONLY			(1ULL << 41)



#define AMD64_EVENTSEL_EVENT	\

	(ARCH_PERFMON_EVENTSEL_EVENT | (0x0FULL << 32))

#define INTEL_ARCH_EVENT_MASK	\
@@ -43,6 +46,9 @@ 
#define AMD64_RAW_EVENT_MASK		\

	(X86_RAW_EVENT_MASK          |  \

	 AMD64_EVENTSEL_EVENT)

#define AMD64_NUM_COUNTERS				4

#define AMD64_NUM_COUNTERS_F15H				6

#define AMD64_NUM_COUNTERS_MAX				AMD64_NUM_COUNTERS_F15H



#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL		0x3c

#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK		(0x00 << 8)
@@ -110,6 +116,35 @@ union cpuid10_edx { 
 */

#define X86_PMC_IDX_FIXED_BTS				(X86_PMC_IDX_FIXED + 16)



/*

 * IBS cpuid feature detection

 */



#define IBS_CPUID_FEATURES		0x8000001b



/*

 * Same bit mask as for IBS cpuid feature flags (Fn8000_001B_EAX), but

 * bit 0 is used to indicate the existence of IBS.

 */

#define IBS_CAPS_AVAIL			(1U<<0)

#define IBS_CAPS_FETCHSAM		(1U<<1)

#define IBS_CAPS_OPSAM			(1U<<2)

#define IBS_CAPS_RDWROPCNT		(1U<<3)

#define IBS_CAPS_OPCNT			(1U<<4)

#define IBS_CAPS_BRNTRGT		(1U<<5)

#define IBS_CAPS_OPCNTEXT		(1U<<6)



#define IBS_CAPS_DEFAULT		(IBS_CAPS_AVAIL		\

					 | IBS_CAPS_FETCHSAM	\

					 | IBS_CAPS_OPSAM)



/*

 * IBS APIC setup

 */

#define IBSCTL				0x1cc

#define IBSCTL_LVT_OFFSET_VALID		(1ULL<<8)

#define IBSCTL_LVT_OFFSET_MASK		0x0F



/* IbsFetchCtl bits/masks */

#define IBS_FETCH_RAND_EN	(1ULL<<57)

#define IBS_FETCH_VAL		(1ULL<<49)
@@ -124,6 +159,8 @@ union cpuid10_edx { 
#define IBS_OP_MAX_CNT		0x0000FFFFULL

#define IBS_OP_MAX_CNT_EXT	0x007FFFFFULL	/* not a register bit mask */



extern u32 get_ibs_caps(void);



#ifdef CONFIG_PERF_EVENTS

extern void perf_events_lapic_init(void);
@@ -159,7 +196,19 @@ extern unsigned long perf_misc_flags(struct pt_regs *regs); 
	);							\

}



struct perf_guest_switch_msr {

	unsigned msr;

	u64 host, guest;

};



extern struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr);

#else

static inline perf_guest_switch_msr *perf_guest_get_msrs(int *nr)

{

	*nr = 0;

	return NULL;

}



static inline void perf_events_lapic_init(void)	{ }

#endif

arch/x86/include/asm/reboot.h

+1 −1
Original line number Diff line number Diff line
@@ -23,7 +23,7 @@ void machine_real_restart(unsigned int type); 
#define MRR_BIOS	0

#define MRR_APM		1



typedef void (*nmi_shootdown_cb)(int, struct die_args*);

typedef void (*nmi_shootdown_cb)(int, struct pt_regs*);

void nmi_shootdown_cpus(nmi_shootdown_cb callback);



#endif /* _ASM_X86_REBOOT_H */

arch/x86/kernel/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -19,7 +19,7 @@ endif 


obj-y			:= process_$(BITS).o signal.o entry_$(BITS).o

obj-y			+= traps.o irq.o irq_$(BITS).o dumpstack_$(BITS).o

obj-y			+= time.o ioport.o ldt.o dumpstack.o

obj-y			+= time.o ioport.o ldt.o dumpstack.o nmi.o

obj-y			+= setup.o x86_init.o i8259.o irqinit.o jump_label.o

obj-$(CONFIG_IRQ_WORK)  += irq_work.o

obj-y			+= probe_roms.o