Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 709d015b authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'drm-intel-next' of git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel 

* 'drm-intel-next' of git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel: (41 commits)
  drm/i915: add HAS_BSD check to i915_getparam
  drm/i915: Honor sync polarity from VBT panel timing descriptors
  drm/i915: Unmask interrupt for render engine on Sandybridge
  drm/i915: Fix PIPE_CONTROL command on Sandybridge
  drm/i915: Fix up address spaces in slow_kernel_write()
  drm/i915: Use non-atomic kmap for slow copy paths
  drm/i915: Avoid moving from CPU domain during pwrite
  drm/i915: Cleanup after failed initialization of ringbuffers
  drm/i915: Reject bind_to_gtt() early if object > aperture
  drm/i915: Check error code whilst moving buffer to GTT domain.
  drm/i915: Remove spurious warning "Failure to install fence"
  drm/i915: Rebind bo if currently bound with incorrect alignment.
  drm/i915: Include pitch in set_base debug statement.
  drm/i915: Only print "nothing to do" debug message as required.
  drm/i915: Propagate error from unbinding an unfenceable object.
  drm/i915: Avoid nesting of domain changes when setting display plane
  drm/i915: Hold the spinlock whilst resetting unpin_work along error path
  drm/i915: Only print an message if there was an error
  drm/i915: Clean up leftover bits from hws move to ring structure.
  drm/i915: Add CxSR support on Pineview DDR3
  ...
parents 08a66859 e3a815fc

drivers/char/agp/intel-gtt.c

+39 −7
Original line number Diff line number Diff line
@@ -1059,7 +1059,7 @@ static void intel_i9xx_setup_flush(void) 
	}

}



static int intel_i915_configure(void)

static int intel_i9xx_configure(void)

{

	struct aper_size_info_fixed *current_size;

	u32 temp;
@@ -1207,6 +1207,38 @@ static int intel_i9xx_fetch_size(void) 
	return 0;

}



static int intel_i915_get_gtt_size(void)

{

	int size;



	if (IS_G33) {

		u16 gmch_ctrl;



		/* G33's GTT size defined in gmch_ctrl */

		pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);

		switch (gmch_ctrl & G33_PGETBL_SIZE_MASK) {

		case G33_PGETBL_SIZE_1M:

			size = 1024;

			break;

		case G33_PGETBL_SIZE_2M:

			size = 2048;

			break;

		default:

			dev_info(&agp_bridge->dev->dev,

				 "unknown page table size 0x%x, assuming 512KB\n",

				(gmch_ctrl & G33_PGETBL_SIZE_MASK));

			size = 512;

		}

	} else {

		/* On previous hardware, the GTT size was just what was

		 * required to map the aperture.

		 */

		size = agp_bridge->driver->fetch_size();

	}



	return KB(size);

}



/* The intel i915 automatically initializes the agp aperture during POST.

 * Use the memory already set aside for in the GTT.

 */
@@ -1216,7 +1248,7 @@ static int intel_i915_create_gatt_table(struct agp_bridge_data *bridge) 
	struct aper_size_info_fixed *size;

	int num_entries;

	u32 temp, temp2;

	int gtt_map_size = 256 * 1024;

	int gtt_map_size;



	size = agp_bridge->current_size;

	page_order = size->page_order;
@@ -1226,8 +1258,8 @@ static int intel_i915_create_gatt_table(struct agp_bridge_data *bridge) 
	pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);

	pci_read_config_dword(intel_private.pcidev, I915_PTEADDR, &temp2);



	if (IS_G33)

	    gtt_map_size = 1024 * 1024; /* 1M on G33 */

	gtt_map_size = intel_i915_get_gtt_size();



	intel_private.gtt = ioremap(temp2, gtt_map_size);

	if (!intel_private.gtt)

		return -ENOMEM;
@@ -1422,7 +1454,7 @@ static const struct agp_bridge_driver intel_915_driver = { 
	.size_type		= FIXED_APER_SIZE,

	.num_aperture_sizes	= 4,

	.needs_scratch_page	= true,

	.configure		= intel_i915_configure,

	.configure		= intel_i9xx_configure,

	.fetch_size		= intel_i9xx_fetch_size,

	.cleanup		= intel_i915_cleanup,

	.mask_memory		= intel_i810_mask_memory,
@@ -1455,7 +1487,7 @@ static const struct agp_bridge_driver intel_i965_driver = { 
	.size_type		= FIXED_APER_SIZE,

	.num_aperture_sizes	= 4,

	.needs_scratch_page	= true,

	.configure		= intel_i915_configure,

	.configure		= intel_i9xx_configure,

	.fetch_size		= intel_i9xx_fetch_size,

	.cleanup		= intel_i915_cleanup,

	.mask_memory		= intel_i965_mask_memory,
@@ -1488,7 +1520,7 @@ static const struct agp_bridge_driver intel_g33_driver = { 
	.size_type		= FIXED_APER_SIZE,

	.num_aperture_sizes	= 4,

	.needs_scratch_page	= true,

	.configure		= intel_i915_configure,

	.configure		= intel_i9xx_configure,

	.fetch_size		= intel_i9xx_fetch_size,

	.cleanup		= intel_i915_cleanup,

	.mask_memory		= intel_i965_mask_memory,

drivers/gpu/drm/i915/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -22,6 +22,7 @@ i915-y := i915_drv.o i915_dma.o i915_irq.o i915_mem.o \ 
	  intel_fb.o \

	  intel_tv.o \

	  intel_dvo.o \

	  intel_ringbuffer.o \

	  intel_overlay.o \

	  dvo_ch7xxx.o \

	  dvo_ch7017.o \

drivers/gpu/drm/i915/i915_debugfs.c

+63 −19
Original line number Diff line number Diff line
@@ -77,7 +77,7 @@ static int i915_gem_object_list_info(struct seq_file *m, void *data) 
	case ACTIVE_LIST:

		seq_printf(m, "Active:\n");

		lock = &dev_priv->mm.active_list_lock;

		head = &dev_priv->mm.active_list;

		head = &dev_priv->render_ring.active_list;

		break;

	case INACTIVE_LIST:

		seq_printf(m, "Inactive:\n");
@@ -129,7 +129,8 @@ static int i915_gem_request_info(struct seq_file *m, void *data) 
	struct drm_i915_gem_request *gem_request;



	seq_printf(m, "Request:\n");

	list_for_each_entry(gem_request, &dev_priv->mm.request_list, list) {

	list_for_each_entry(gem_request, &dev_priv->render_ring.request_list,

			list) {

		seq_printf(m, "    %d @ %d\n",

			   gem_request->seqno,

			   (int) (jiffies - gem_request->emitted_jiffies));
@@ -143,9 +144,9 @@ static int i915_gem_seqno_info(struct seq_file *m, void *data) 
	struct drm_device *dev = node->minor->dev;

	drm_i915_private_t *dev_priv = dev->dev_private;



	if (dev_priv->hw_status_page != NULL) {

	if (dev_priv->render_ring.status_page.page_addr != NULL) {

		seq_printf(m, "Current sequence: %d\n",

			   i915_get_gem_seqno(dev));

			   i915_get_gem_seqno(dev,  &dev_priv->render_ring));

	} else {

		seq_printf(m, "Current sequence: hws uninitialized\n");

	}
@@ -195,9 +196,9 @@ static int i915_interrupt_info(struct seq_file *m, void *data) 
	}

	seq_printf(m, "Interrupts received: %d\n",

		   atomic_read(&dev_priv->irq_received));

	if (dev_priv->hw_status_page != NULL) {

	if (dev_priv->render_ring.status_page.page_addr != NULL) {

		seq_printf(m, "Current sequence:    %d\n",

			   i915_get_gem_seqno(dev));

			   i915_get_gem_seqno(dev,  &dev_priv->render_ring));

	} else {

		seq_printf(m, "Current sequence:    hws uninitialized\n");

	}
@@ -251,7 +252,7 @@ static int i915_hws_info(struct seq_file *m, void *data) 
	int i;

	volatile u32 *hws;



	hws = (volatile u32 *)dev_priv->hw_status_page;

	hws = (volatile u32 *)dev_priv->render_ring.status_page.page_addr;

	if (hws == NULL)

		return 0;
@@ -287,7 +288,8 @@ static int i915_batchbuffer_info(struct seq_file *m, void *data) 


	spin_lock(&dev_priv->mm.active_list_lock);



	list_for_each_entry(obj_priv, &dev_priv->mm.active_list, list) {

	list_for_each_entry(obj_priv, &dev_priv->render_ring.active_list,

			list) {

		obj = &obj_priv->base;

		if (obj->read_domains & I915_GEM_DOMAIN_COMMAND) {

		    ret = i915_gem_object_get_pages(obj, 0);
@@ -317,14 +319,14 @@ static int i915_ringbuffer_data(struct seq_file *m, void *data) 
	u8 *virt;

	uint32_t *ptr, off;



	if (!dev_priv->ring.ring_obj) {

	if (!dev_priv->render_ring.gem_object) {

		seq_printf(m, "No ringbuffer setup\n");

		return 0;

	}



	virt = dev_priv->ring.virtual_start;

	virt = dev_priv->render_ring.virtual_start;



	for (off = 0; off < dev_priv->ring.Size; off += 4) {

	for (off = 0; off < dev_priv->render_ring.size; off += 4) {

		ptr = (uint32_t *)(virt + off);

		seq_printf(m, "%08x :  %08x\n", off, *ptr);

	}
@@ -344,7 +346,7 @@ static int i915_ringbuffer_info(struct seq_file *m, void *data) 


	seq_printf(m, "RingHead :  %08x\n", head);

	seq_printf(m, "RingTail :  %08x\n", tail);

	seq_printf(m, "RingSize :  %08lx\n", dev_priv->ring.Size);

	seq_printf(m, "RingSize :  %08lx\n", dev_priv->render_ring.size);

	seq_printf(m, "Acthd :     %08x\n", I915_READ(IS_I965G(dev) ? ACTHD_I965 : ACTHD));



	return 0;
@@ -489,11 +491,14 @@ static int i915_cur_delayinfo(struct seq_file *m, void *unused) 
	struct drm_device *dev = node->minor->dev;

	drm_i915_private_t *dev_priv = dev->dev_private;

	u16 rgvswctl = I915_READ16(MEMSWCTL);

	u16 rgvstat = I915_READ16(MEMSTAT_ILK);



	seq_printf(m, "Last command: 0x%01x\n", (rgvswctl >> 13) & 0x3);

	seq_printf(m, "Command status: %d\n", (rgvswctl >> 12) & 1);

	seq_printf(m, "P%d DELAY 0x%02x\n", (rgvswctl >> 8) & 0xf,

		   rgvswctl & 0x3f);

	seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);

	seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);

	seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>

		   MEMSTAT_VID_SHIFT);

	seq_printf(m, "Current P-state: %d\n",

		   (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);



	return 0;

}
@@ -508,7 +513,8 @@ static int i915_delayfreq_table(struct seq_file *m, void *unused) 


	for (i = 0; i < 16; i++) {

		delayfreq = I915_READ(PXVFREQ_BASE + i * 4);

		seq_printf(m, "P%02dVIDFREQ: 0x%08x\n", i, delayfreq);

		seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq,

			   (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT);

	}



	return 0;
@@ -541,6 +547,8 @@ static int i915_drpc_info(struct seq_file *m, void *unused) 
	struct drm_device *dev = node->minor->dev;

	drm_i915_private_t *dev_priv = dev->dev_private;

	u32 rgvmodectl = I915_READ(MEMMODECTL);

	u32 rstdbyctl = I915_READ(MCHBAR_RENDER_STANDBY);

	u16 crstandvid = I915_READ16(CRSTANDVID);



	seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?

		   "yes" : "no");
@@ -555,9 +563,13 @@ static int i915_drpc_info(struct seq_file *m, void *unused) 
		   rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");

	seq_printf(m, "Starting frequency: P%d\n",

		   (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);

	seq_printf(m, "Max frequency: P%d\n",

	seq_printf(m, "Max P-state: P%d\n",

		   (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);

	seq_printf(m, "Min frequency: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));

	seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));

	seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));

	seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));

	seq_printf(m, "Render standby enabled: %s\n",

		   (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");



	return 0;

}
@@ -621,6 +633,36 @@ static int i915_sr_status(struct seq_file *m, void *unused) 
	return 0;

}



static int i915_emon_status(struct seq_file *m, void *unused)

{

	struct drm_info_node *node = (struct drm_info_node *) m->private;

	struct drm_device *dev = node->minor->dev;

	drm_i915_private_t *dev_priv = dev->dev_private;

	unsigned long temp, chipset, gfx;



	temp = i915_mch_val(dev_priv);

	chipset = i915_chipset_val(dev_priv);

	gfx = i915_gfx_val(dev_priv);



	seq_printf(m, "GMCH temp: %ld\n", temp);

	seq_printf(m, "Chipset power: %ld\n", chipset);

	seq_printf(m, "GFX power: %ld\n", gfx);

	seq_printf(m, "Total power: %ld\n", chipset + gfx);



	return 0;

}



static int i915_gfxec(struct seq_file *m, void *unused)

{

	struct drm_info_node *node = (struct drm_info_node *) m->private;

	struct drm_device *dev = node->minor->dev;

	drm_i915_private_t *dev_priv = dev->dev_private;



	seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4));



	return 0;

}



static int

i915_wedged_open(struct inode *inode,

		 struct file *filp)
@@ -743,6 +785,8 @@ static struct drm_info_list i915_debugfs_list[] = { 
	{"i915_delayfreq_table", i915_delayfreq_table, 0},

	{"i915_inttoext_table", i915_inttoext_table, 0},

	{"i915_drpc_info", i915_drpc_info, 0},

	{"i915_emon_status", i915_emon_status, 0},

	{"i915_gfxec", i915_gfxec, 0},

	{"i915_fbc_status", i915_fbc_status, 0},

	{"i915_sr_status", i915_sr_status, 0},

};

drivers/gpu/drm/i915/i915_dma.c

+582 −129

File changed.

Preview size limit exceeded, changes collapsed.

drivers/gpu/drm/i915/i915_drv.c

+24 −46
Original line number Diff line number Diff line
@@ -60,95 +60,95 @@ extern int intel_agp_enabled; 
	.subdevice = PCI_ANY_ID,		\

	.driver_data = (unsigned long) info }



const static struct intel_device_info intel_i830_info = {

static const struct intel_device_info intel_i830_info = {

	.is_i8xx = 1, .is_mobile = 1, .cursor_needs_physical = 1,

};



const static struct intel_device_info intel_845g_info = {

static const struct intel_device_info intel_845g_info = {

	.is_i8xx = 1,

};



const static struct intel_device_info intel_i85x_info = {

static const struct intel_device_info intel_i85x_info = {

	.is_i8xx = 1, .is_i85x = 1, .is_mobile = 1,

	.cursor_needs_physical = 1,

};



const static struct intel_device_info intel_i865g_info = {

static const struct intel_device_info intel_i865g_info = {

	.is_i8xx = 1,

};



const static struct intel_device_info intel_i915g_info = {

static const struct intel_device_info intel_i915g_info = {

	.is_i915g = 1, .is_i9xx = 1, .cursor_needs_physical = 1,

};

const static struct intel_device_info intel_i915gm_info = {

static const struct intel_device_info intel_i915gm_info = {

	.is_i9xx = 1,  .is_mobile = 1,

	.cursor_needs_physical = 1,

};

const static struct intel_device_info intel_i945g_info = {

static const struct intel_device_info intel_i945g_info = {

	.is_i9xx = 1, .has_hotplug = 1, .cursor_needs_physical = 1,

};

const static struct intel_device_info intel_i945gm_info = {

static const struct intel_device_info intel_i945gm_info = {

	.is_i945gm = 1, .is_i9xx = 1, .is_mobile = 1,

	.has_hotplug = 1, .cursor_needs_physical = 1,

};



const static struct intel_device_info intel_i965g_info = {

static const struct intel_device_info intel_i965g_info = {

	.is_i965g = 1, .is_i9xx = 1, .has_hotplug = 1,

};



const static struct intel_device_info intel_i965gm_info = {

static const struct intel_device_info intel_i965gm_info = {

	.is_i965g = 1, .is_mobile = 1, .is_i965gm = 1, .is_i9xx = 1,

	.is_mobile = 1, .has_fbc = 1, .has_rc6 = 1,

	.has_hotplug = 1,

};



const static struct intel_device_info intel_g33_info = {

static const struct intel_device_info intel_g33_info = {

	.is_g33 = 1, .is_i9xx = 1, .need_gfx_hws = 1,

	.has_hotplug = 1,

};



const static struct intel_device_info intel_g45_info = {

static const struct intel_device_info intel_g45_info = {

	.is_i965g = 1, .is_g4x = 1, .is_i9xx = 1, .need_gfx_hws = 1,

	.has_pipe_cxsr = 1,

	.has_hotplug = 1,

};



const static struct intel_device_info intel_gm45_info = {

static const struct intel_device_info intel_gm45_info = {

	.is_i965g = 1, .is_mobile = 1, .is_g4x = 1, .is_i9xx = 1,

	.is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1, .has_rc6 = 1,

	.has_pipe_cxsr = 1,

	.has_hotplug = 1,

};



const static struct intel_device_info intel_pineview_info = {

static const struct intel_device_info intel_pineview_info = {

	.is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .is_i9xx = 1,

	.need_gfx_hws = 1,

	.has_hotplug = 1,

};



const static struct intel_device_info intel_ironlake_d_info = {

static const struct intel_device_info intel_ironlake_d_info = {

	.is_ironlake = 1, .is_i965g = 1, .is_i9xx = 1, .need_gfx_hws = 1,

	.has_pipe_cxsr = 1,

	.has_hotplug = 1,

};



const static struct intel_device_info intel_ironlake_m_info = {

static const struct intel_device_info intel_ironlake_m_info = {

	.is_ironlake = 1, .is_mobile = 1, .is_i965g = 1, .is_i9xx = 1,

	.need_gfx_hws = 1, .has_rc6 = 1,

	.has_hotplug = 1,

};



const static struct intel_device_info intel_sandybridge_d_info = {

static const struct intel_device_info intel_sandybridge_d_info = {

	.is_i965g = 1, .is_i9xx = 1, .need_gfx_hws = 1,

	.has_hotplug = 1, .is_gen6 = 1,

};



const static struct intel_device_info intel_sandybridge_m_info = {

static const struct intel_device_info intel_sandybridge_m_info = {

	.is_i965g = 1, .is_mobile = 1, .is_i9xx = 1, .need_gfx_hws = 1,

	.has_hotplug = 1, .is_gen6 = 1,

};



const static struct pci_device_id pciidlist[] = {

static const struct pci_device_id pciidlist[] = {

	INTEL_VGA_DEVICE(0x3577, &intel_i830_info),

	INTEL_VGA_DEVICE(0x2562, &intel_845g_info),

	INTEL_VGA_DEVICE(0x3582, &intel_i85x_info),
@@ -340,7 +340,7 @@ int i965_reset(struct drm_device *dev, u8 flags) 
	/*

	 * Clear request list

	 */

	i915_gem_retire_requests(dev);

	i915_gem_retire_requests(dev, &dev_priv->render_ring);



	if (need_display)

		i915_save_display(dev);
@@ -370,6 +370,7 @@ int i965_reset(struct drm_device *dev, u8 flags) 
		}

	} else {

		DRM_ERROR("Error occurred. Don't know how to reset this chip.\n");

		mutex_unlock(&dev->struct_mutex);

		return -ENODEV;

	}
@@ -389,32 +390,9 @@ int i965_reset(struct drm_device *dev, u8 flags) 
	 */

	if (drm_core_check_feature(dev, DRIVER_MODESET) ||

			!dev_priv->mm.suspended) {

		drm_i915_ring_buffer_t *ring = &dev_priv->ring;

		struct drm_gem_object *obj = ring->ring_obj;

		struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);

		struct intel_ring_buffer *ring = &dev_priv->render_ring;

		dev_priv->mm.suspended = 0;



		/* Stop the ring if it's running. */

		I915_WRITE(PRB0_CTL, 0);

		I915_WRITE(PRB0_TAIL, 0);

		I915_WRITE(PRB0_HEAD, 0);



		/* Initialize the ring. */

		I915_WRITE(PRB0_START, obj_priv->gtt_offset);

		I915_WRITE(PRB0_CTL,

			   ((obj->size - 4096) & RING_NR_PAGES) |

			   RING_NO_REPORT |

			   RING_VALID);

		if (!drm_core_check_feature(dev, DRIVER_MODESET))

			i915_kernel_lost_context(dev);

		else {

			ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;

			ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;

			ring->space = ring->head - (ring->tail + 8);

			if (ring->space < 0)

				ring->space += ring->Size;

		}



		ring->init(dev, ring);

		mutex_unlock(&dev->struct_mutex);

		drm_irq_uninstall(dev);

		drm_irq_install(dev);