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Commit 709b126d authored by Dinesh K Garg's avatar Dinesh K Garg
Browse files

ARM: dts: msm: Add clocks, bus vote & regulator to ICE for msm8996 



New ICE hardware requires power regulators, clocks, bus vote to be
enabled and set properly before key registers can be read/written.
Earlier, caller was explicitly doing this job. Now, it is becoming
complex and hence moving all ICE setup related functionalities to
ICE driver.

Change-Id: I8375ef667eb5f231c2b308f0f82a9cf413c32354
Signed-off-by: default avatarDinesh K Garg <dineshg@codeaurora.org>
parent 125aa701

arch/arm/boot/dts/qcom/msm8996.dtsi

+35 −5
Original line number Diff line number Diff line
@@ -1176,10 +1176,29 @@ 
		interrupt-names = "ufs_ice_nonsec_level_irq", "ufs_ice_sec_level_irq";

		interrupts = <0 258 0>, <0 257 0>;

		qcom,enable-ice-clk;

		clock-names = "ice_core_clk_src", "ice_core_clk";

		clocks = <&clock_gcc clk_ufs_ice_core_clk_src>,

		clock-names =   "ufs_core_clk_src",

				"ufs_core_clk",

				"bus_clk",

				"iface_clk",

				"ice_core_clk_src",

				"ice_core_clk";

		clocks = <&clock_gcc clk_ufs_axi_clk_src>,

			 <&clock_gcc clk_gcc_ufs_axi_clk>,

			 <&clock_gcc clk_gcc_sys_noc_ufs_axi_clk>,

			 <&clock_gcc clk_gcc_ufs_ahb_clk>,

			 <&clock_gcc clk_ufs_ice_core_clk_src>,

			 <&clock_gcc clk_gcc_ufs_ice_core_clk>;

		qcom,op-freq-hz = <300000000>, <0>;

		qcom,op-freq-hz = <0>, <0>, <0>,<0>,

				 <300000000>, <0>;

		vdd-hba-supply = <&gdsc_ufs>;

		qcom,msm-bus,name = "ufs_ice_noc";

		qcom,msm-bus,num-cases = <2>;

		qcom,msm-bus,num-paths = <1>;

		qcom,msm-bus,vectors-KBps =

				<1 650 0 0>,    /* No vote */

				<1 650 1000 0>; /* Max. bandwidth */

		qcom,bus-vector-names = "MIN",

					"MAX";

		qcom,instance-type = "ufs";

		status = "disabled";

	};
@@ -1190,10 +1209,21 @@ 
		interrupt-names = "sdcc_ice_nonsec_level_irq", "sdcc_ice_sec_level_irq";

		interrupts = <0 461 0>, <0 460 0>;

		qcom,enable-ice-clk;

		clock-names = "ice_core_clk_src", "ice_core_clk";

		clock-names = "ice_core_clk_src", "ice_core_clk",

				"bus_clk", "iface_clk";

		clocks = <&clock_gcc clk_sdcc1_ice_core_clk_src>,

			 <&clock_gcc clk_gcc_sdcc1_ice_core_clk>;

			 <&clock_gcc clk_gcc_sdcc1_ice_core_clk>,

			 <&clock_gcc clk_gcc_sdcc1_apps_clk>,

			 <&clock_gcc clk_gcc_sdcc1_ahb_clk>;

		qcom,op-freq-hz = <300000000>, <0>;

		qcom,msm-bus,name = "sdcc_ice_noc";

		qcom,msm-bus,num-cases = <2>;

		qcom,msm-bus,num-paths = <1>;

		qcom,msm-bus,vectors-KBps =

			<78 512 0 0>,    /* No vote */

			<78 512 1000 0>; /* Max. bandwidth */

		qcom,bus-vector-names = "MIN",

					"MAX";

		qcom,instance-type = "sdcc";

		status = "disabled";

	};