Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 70103814 authored by Russell King's avatar Russell King Committed by Russell King
Browse files

Merge branch 'nomadik' into devel-stable

parents 4abf27ad c2b45547

arch/arm/Kconfig

+16 −0
Original line number Diff line number Diff line
@@ -338,6 +338,20 @@ config ARCH_H720X 
	help

	  This enables support for systems based on the Hynix HMS720x



config ARCH_NOMADIK

	bool "STMicroelectronics Nomadik"

	select ARM_AMBA

	select ARM_VIC

	select CPU_ARM926T

	select HAVE_CLK

	select COMMON_CLKDEV

	select GENERIC_TIME

	select GENERIC_CLOCKEVENTS

	select GENERIC_GPIO

	select ARCH_REQUIRE_GPIOLIB

	help

	  Support for the Nomadik platform by ST-Ericsson



config ARCH_IOP13XX

	bool "IOP13xx-based"

	depends on MMU
@@ -745,6 +759,8 @@ source "arch/arm/mach-at91/Kconfig" 


source "arch/arm/plat-mxc/Kconfig"



source "arch/arm/mach-nomadik/Kconfig"



source "arch/arm/mach-netx/Kconfig"



source "arch/arm/mach-ns9xxx/Kconfig"

arch/arm/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -145,6 +145,7 @@ machine-$(CONFIG_ARCH_MX2) := mx2 
machine-$(CONFIG_ARCH_MX25)		:= mx25

machine-$(CONFIG_ARCH_MX3)		:= mx3

machine-$(CONFIG_ARCH_NETX)		:= netx

machine-$(CONFIG_ARCH_NOMADIK)		:= nomadik

machine-$(CONFIG_ARCH_NS9XXX)		:= ns9xxx

machine-$(CONFIG_ARCH_OMAP1)		:= omap1

machine-$(CONFIG_ARCH_OMAP2)		:= omap2

arch/arm/common/vic.c

+98 −1
Original line number Diff line number Diff line
@@ -26,6 +26,15 @@ 
#include <asm/mach/irq.h>

#include <asm/hardware/vic.h>



static void vic_ack_irq(unsigned int irq)

{

	void __iomem *base = get_irq_chip_data(irq);

	irq &= 31;

	writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);

	/* moreover, clear the soft-triggered, in case it was the reason */

	writel(1 << irq, base + VIC_INT_SOFT_CLEAR);

}



static void vic_mask_irq(unsigned int irq)

{

	void __iomem *base = get_irq_chip_data(irq);
@@ -253,12 +262,21 @@ static inline void vic_pm_register(void __iomem *base, unsigned int irq, u32 arg 


static struct irq_chip vic_chip = {

	.name	= "VIC",

	.ack	= vic_mask_irq,

	.ack	= vic_ack_irq,

	.mask	= vic_mask_irq,

	.unmask	= vic_unmask_irq,

	.set_wake = vic_set_wake,

};



/* The PL190 cell from ARM has been modified by ST, so handle both here */

static void vik_init_st(void __iomem *base, unsigned int irq_start,

			 u32 vic_sources);



enum vic_vendor {

	VENDOR_ARM = 0x41,

	VENDOR_ST = 0x80,

};



/**

 * vic_init - initialise a vectored interrupt controller

 * @base: iomem base address
@@ -270,6 +288,28 @@ void __init vic_init(void __iomem *base, unsigned int irq_start, 
		     u32 vic_sources, u32 resume_sources)

{

	unsigned int i;

	u32 cellid = 0;

	enum vic_vendor vendor;



	/* Identify which VIC cell this one is, by reading the ID */

	for (i = 0; i < 4; i++) {

		u32 addr = ((u32)base & PAGE_MASK) + 0xfe0 + (i * 4);

		cellid |= (readl(addr) & 0xff) << (8 * i);

	}

	vendor = (cellid >> 12) & 0xff;

	printk(KERN_INFO "VIC @%p: id 0x%08x, vendor 0x%02x\n",

	       base, cellid, vendor);



	switch(vendor) {

	case VENDOR_ST:

		vik_init_st(base, irq_start, vic_sources);

		return;

	default:

		printk(KERN_WARNING "VIC: unknown vendor, continuing anyways\n");

		/* fall through */

	case VENDOR_ARM:

		break;

	}



	/* Disable all interrupts initially. */
@@ -306,3 +346,60 @@ void __init vic_init(void __iomem *base, unsigned int irq_start, 


	vic_pm_register(base, irq_start, resume_sources);

}



/*

 * The PL190 cell from ARM has been modified by ST to handle 64 interrupts.

 * The original cell has 32 interrupts, while the modified one has 64,

 * replocating two blocks 0x00..0x1f in 0x20..0x3f. In that case

 * the probe function is called twice, with base set to offset 000

 *  and 020 within the page. We call this "second block".

 */

static void __init vik_init_st(void __iomem *base, unsigned int irq_start,

				u32 vic_sources)

{

	unsigned int i;

	int vic_2nd_block = ((unsigned long)base & ~PAGE_MASK) != 0;



	/* Disable all interrupts initially. */



	writel(0, base + VIC_INT_SELECT);

	writel(0, base + VIC_INT_ENABLE);

	writel(~0, base + VIC_INT_ENABLE_CLEAR);

	writel(0, base + VIC_IRQ_STATUS);

	writel(0, base + VIC_ITCR);

	writel(~0, base + VIC_INT_SOFT_CLEAR);



	/*

	 * Make sure we clear all existing interrupts. The vector registers

	 * in this cell are after the second block of general registers,

	 * so we can address them using standard offsets, but only from

	 * the second base address, which is 0x20 in the page

	 */

	if (vic_2nd_block) {

		writel(0, base + VIC_PL190_VECT_ADDR);

		for (i = 0; i < 19; i++) {

			unsigned int value;



			value = readl(base + VIC_PL190_VECT_ADDR);

			writel(value, base + VIC_PL190_VECT_ADDR);

		}

		/* ST has 16 vectors as well, but we don't enable them by now */

		for (i = 0; i < 16; i++) {

			void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4);

			writel(0, reg);

		}



		writel(32, base + VIC_PL190_DEF_VECT_ADDR);

	}



	for (i = 0; i < 32; i++) {

		if (vic_sources & (1 << i)) {

			unsigned int irq = irq_start + i;



			set_irq_chip(irq, &vic_chip);

			set_irq_chip_data(irq, base);

			set_irq_handler(irq, handle_level_irq);

			set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);

		}

	}

}