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Commit 6f8b26f9 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "FROMLIST: arm64: mm: Use non-global mappings for kernel space"

parents e4a2c28d 5c51481c

arch/arm64/include/asm/assembler.h

+20 −0
Original line number Diff line number Diff line
@@ -321,4 +321,24 @@ lr .req x30 // link register 
	mrs	\rd, sp_el0

	.endm



	/*

	 * mov_q - move an immediate constant into a 64-bit register using

	 *         between 2 and 4 movz/movk instructions (depending on the

	 *         magnitude and sign of the operand)

	 */

	.macro	mov_q, reg, val

	.if (((\val) >> 31) == 0 || ((\val) >> 31) == 0x1ffffffff)

	movz	\reg, :abs_g1_s:\val

	.else

	.if (((\val) >> 47) == 0 || ((\val) >> 47) == 0x1ffff)

	movz	\reg, :abs_g2_s:\val

	.else

	movz	\reg, :abs_g3:\val

	movk	\reg, :abs_g2_nc:\val

	.endif

	movk	\reg, :abs_g1_nc:\val

	.endif

	movk	\reg, :abs_g0_nc:\val

	.endm



#endif	/* __ASM_ASSEMBLER_H */

arch/arm64/include/asm/kernel-pgtable.h

+10 −2
Original line number Diff line number Diff line
@@ -61,8 +61,16 @@ 
/*

 * Initial memory map attributes.

 */

#define SWAPPER_PTE_FLAGS	(PTE_TYPE_PAGE | PTE_AF | PTE_SHARED)

#define SWAPPER_PMD_FLAGS	(PMD_TYPE_SECT | PMD_SECT_AF | PMD_SECT_S)

#define _SWAPPER_PTE_FLAGS	(PTE_TYPE_PAGE | PTE_AF | PTE_SHARED)

#define _SWAPPER_PMD_FLAGS	(PMD_TYPE_SECT | PMD_SECT_AF | PMD_SECT_S)



#ifdef CONFIG_UNMAP_KERNEL_AT_EL0

#define SWAPPER_PTE_FLAGS	(_SWAPPER_PTE_FLAGS | PTE_NG)

#define SWAPPER_PMD_FLAGS	(_SWAPPER_PMD_FLAGS | PMD_SECT_NG)

#else

#define SWAPPER_PTE_FLAGS	_SWAPPER_PTE_FLAGS

#define SWAPPER_PMD_FLAGS	_SWAPPER_PMD_FLAGS

#endif



#ifdef CONFIG_ARM64_64K_PAGES

#define SWAPPER_MM_MMUFLAGS	(PTE_ATTRINDX(MT_NORMAL) | SWAPPER_PTE_FLAGS)

arch/arm64/include/asm/pgtable.h

+14 −4
Original line number Diff line number Diff line
@@ -63,8 +63,16 @@ extern void __pmd_error(const char *file, int line, unsigned long val); 
extern void __pud_error(const char *file, int line, unsigned long val);

extern void __pgd_error(const char *file, int line, unsigned long val);



#define PROT_DEFAULT		(PTE_TYPE_PAGE | PTE_AF | PTE_SHARED)

#define PROT_SECT_DEFAULT	(PMD_TYPE_SECT | PMD_SECT_AF | PMD_SECT_S)

#define _PROT_DEFAULT		(PTE_TYPE_PAGE | PTE_AF | PTE_SHARED)

#define _PROT_SECT_DEFAULT	(PMD_TYPE_SECT | PMD_SECT_AF | PMD_SECT_S)



#ifdef CONFIG_UNMAP_KERNEL_AT_EL0

#define PROT_DEFAULT		(_PROT_DEFAULT | PTE_NG)

#define PROT_SECT_DEFAULT	(_PROT_SECT_DEFAULT | PMD_SECT_NG)

#else

#define PROT_DEFAULT		_PROT_DEFAULT

#define PROT_SECT_DEFAULT	_PROT_SECT_DEFAULT

#endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */



#define PROT_DEVICE_nGnRnE	(PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_ATTRINDX(MT_DEVICE_nGnRnE))

#define PROT_DEVICE_nGnRE	(PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_ATTRINDX(MT_DEVICE_nGnRE))
@@ -76,17 +84,19 @@ extern void __pgd_error(const char *file, int line, unsigned long val); 
#define PROT_SECT_NORMAL_EXEC	(PROT_SECT_DEFAULT | PMD_SECT_UXN | PMD_ATTRINDX(MT_NORMAL))



#define _PAGE_DEFAULT		(PROT_DEFAULT | PTE_ATTRINDX(MT_NORMAL))

#define _HYP_PAGE_DEFAULT	(_PAGE_DEFAULT & ~PTE_NG)



#define PAGE_KERNEL		__pgprot(_PAGE_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE)

#define PAGE_KERNEL_RO		__pgprot(_PAGE_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_RDONLY)

#define PAGE_KERNEL_EXEC	__pgprot(_PAGE_DEFAULT | PTE_UXN | PTE_DIRTY | PTE_WRITE)



#define PAGE_HYP		__pgprot(_PAGE_DEFAULT | PTE_HYP)

#define PAGE_HYP		__pgprot(_HYP_PAGE_DEFAULT | PTE_HYP)

#define PAGE_HYP_DEVICE		__pgprot(PROT_DEVICE_nGnRE | PTE_HYP)



#define PAGE_S2			__pgprot(PROT_DEFAULT | PTE_S2_MEMATTR(MT_S2_NORMAL) | PTE_S2_RDONLY)

#define PAGE_S2_DEVICE		__pgprot(PROT_DEFAULT | PTE_S2_MEMATTR(MT_S2_DEVICE_nGnRE) | PTE_S2_RDONLY | PTE_UXN)



#define PAGE_NONE		__pgprot(((_PAGE_DEFAULT) & ~PTE_TYPE_MASK) | PTE_PROT_NONE | PTE_PXN | PTE_UXN)

#define PAGE_NONE		__pgprot(((_PAGE_DEFAULT) & ~PTE_TYPE_MASK) | PTE_PROT_NONE | PTE_NG | PTE_PXN | PTE_UXN)

#define PAGE_SHARED		__pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_UXN | PTE_WRITE)

#define PAGE_SHARED_EXEC	__pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_WRITE)

#define PAGE_COPY		__pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_UXN)

arch/arm64/include/asm/tlbflush.h

+28 −10
Original line number Diff line number Diff line
@@ -24,6 +24,24 @@ 
#include <linux/sched.h>

#include <asm/cputype.h>



/*

 * Raw TLBI operations.

 *

 * Where necessary, use the __tlbi() macro to avoid asm()

 * boilerplate. Drivers and most kernel code should use the TLB

 * management routines in preference to the macro below.

 *

 * The macro can be used as __tlbi(op) or __tlbi(op, arg), depending

 * on whether a particular TLBI operation takes an argument or

 * not. The macros handles invoking the asm with or without the

 * register argument as appropriate.

 */

#define __TLBI_0(op, arg)		asm ("tlbi " #op)

#define __TLBI_1(op, arg)		asm ("tlbi " #op ", %0" : : "r" (arg))

#define __TLBI_N(op, arg, n, ...)	__TLBI_##n(op, arg)



#define __tlbi(op, ...)		__TLBI_N(op, ##__VA_ARGS__, 1, 0)



/*

 *	TLB Management

 *	==============
@@ -66,7 +84,7 @@ 
static inline void local_flush_tlb_all(void)

{

	dsb(nshst);

	asm("tlbi	vmalle1");

	__tlbi(vmalle1);

	dsb(nsh);

	isb();

}
@@ -74,7 +92,7 @@ static inline void local_flush_tlb_all(void) 
static inline void flush_tlb_all(void)

{

	dsb(ishst);

	asm("tlbi	vmalle1is");

	__tlbi(vmalle1is);

	dsb(ish);

	isb();

}
@@ -83,14 +101,14 @@ static inline void flush_tlb_mm(struct mm_struct *mm) 
{

#ifdef CONFIG_ARCH_MSM8994_V1_TLBI_WA

	dsb();

	asm("tlbi	vmalle1is");

	__tlbi(vmalle1is);

	dsb();

	isb();

#else

	unsigned long asid = (unsigned long)ASID(mm) << 48;



	dsb(ishst);

	asm("tlbi	aside1is, %0" : : "r" (asid));

	__tlbi(aside1is, asid);

	dsb(ish);

#endif

}
@@ -100,7 +118,7 @@ static inline void flush_tlb_page(struct vm_area_struct *vma, 
{

#ifdef CONFIG_ARCH_MSM8994_V1_TLBI_WA

	dsb();

	asm("tlbi	vmalle1is");

	__tlbi(vmalle1is);

	dsb();

	isb();

#else
@@ -108,7 +126,7 @@ static inline void flush_tlb_page(struct vm_area_struct *vma, 
		((unsigned long)ASID(vma->vm_mm) << 48);



	dsb(ishst);

	asm("tlbi	vale1is, %0" : : "r" (addr));

	__tlbi(vale1is, addr);

	dsb(ish);

#endif

}
@@ -137,9 +155,9 @@ static inline void __flush_tlb_range(struct vm_area_struct *vma, 
	dsb(ishst);

	for (addr = start; addr < end; addr += 1 << (PAGE_SHIFT - 12)) {

		if (last_level)

			asm("tlbi vale1is, %0" : : "r"(addr));

			__tlbi(vale1is, addr);

		else

			asm("tlbi vae1is, %0" : : "r"(addr));

			__tlbi(vae1is, addr);

	}

	dsb(ish);

}
@@ -164,7 +182,7 @@ static inline void flush_tlb_kernel_range(unsigned long start, unsigned long end 


	dsb(ishst);

	for (addr = start; addr < end; addr += 1 << (PAGE_SHIFT - 12))

		asm("tlbi vaae1is, %0" : : "r"(addr));

		__tlbi(vaae1is, addr);

	dsb(ish);

	isb();

}
@@ -178,7 +196,7 @@ static inline void __flush_tlb_pgtable(struct mm_struct *mm, 
{

	unsigned long addr = uaddr >> 12 | (ASID(mm) << 48);



	asm("tlbi	vae1is, %0" : : "r" (addr));

	__tlbi(vae1is, addr);

	dsb(ish);

}

arch/arm64/kernel/entry.S

+26 −21
Original line number Diff line number Diff line
@@ -69,8 +69,13 @@ 
#define BAD_FIQ		2

#define BAD_ERROR	3



	.macro	kernel_entry, el, regsize = 64

	.macro kernel_ventry	label

	.align 7

	sub	sp, sp, #S_FRAME_SIZE

	b	\label

	.endm



	.macro	kernel_entry, el, regsize = 64

	.if	\regsize == 32

	mov	w0, w0				// zero upper 32 bits of x0

	.endif
@@ -270,31 +275,31 @@ tsk .req x28 // current thread_info 


	.align	11

ENTRY(vectors)

	ventry	el1_sync_invalid		// Synchronous EL1t

	ventry	el1_irq_invalid			// IRQ EL1t

	ventry	el1_fiq_invalid			// FIQ EL1t

	ventry	el1_error_invalid		// Error EL1t

	kernel_ventry	el1_sync_invalid		// Synchronous EL1t

	kernel_ventry	el1_irq_invalid			// IRQ EL1t

	kernel_ventry	el1_fiq_invalid			// FIQ EL1t

	kernel_ventry	el1_error_invalid		// Error EL1t



	ventry	el1_sync			// Synchronous EL1h

	ventry	el1_irq				// IRQ EL1h

	ventry	el1_fiq_invalid			// FIQ EL1h

	ventry	el1_error_invalid		// Error EL1h

	kernel_ventry	el1_sync			// Synchronous EL1h

	kernel_ventry	el1_irq				// IRQ EL1h

	kernel_ventry	el1_fiq_invalid			// FIQ EL1h

	kernel_ventry	el1_error_invalid		// Error EL1h



	ventry	el0_sync			// Synchronous 64-bit EL0

	ventry	el0_irq				// IRQ 64-bit EL0

	ventry	el0_fiq_invalid			// FIQ 64-bit EL0

	ventry	el0_error_invalid		// Error 64-bit EL0

	kernel_ventry	el0_sync			// Synchronous 64-bit EL0

	kernel_ventry	el0_irq				// IRQ 64-bit EL0

	kernel_ventry	el0_fiq_invalid			// FIQ 64-bit EL0

	kernel_ventry	el0_error_invalid		// Error 64-bit EL0



#ifdef CONFIG_COMPAT

	ventry	el0_sync_compat			// Synchronous 32-bit EL0

	ventry	el0_irq_compat			// IRQ 32-bit EL0

	ventry	el0_fiq_invalid_compat		// FIQ 32-bit EL0

	ventry	el0_error_invalid_compat	// Error 32-bit EL0

	kernel_ventry	el0_sync_compat			// Synchronous 32-bit EL0

	kernel_ventry	el0_irq_compat			// IRQ 32-bit EL0

	kernel_ventry	el0_fiq_invalid_compat		// FIQ 32-bit EL0

	kernel_ventry	el0_error_invalid_compat	// Error 32-bit EL0

#else

	ventry	el0_sync_invalid		// Synchronous 32-bit EL0

	ventry	el0_irq_invalid			// IRQ 32-bit EL0

	ventry	el0_fiq_invalid			// FIQ 32-bit EL0

	ventry	el0_error_invalid		// Error 32-bit EL0

	kernel_ventry	el0_sync_invalid		// Synchronous 32-bit EL0

	kernel_ventry	el0_irq_invalid			// IRQ 32-bit EL0

	kernel_ventry	el0_fiq_invalid			// FIQ 32-bit EL0

	kernel_ventry	el0_error_invalid		// Error 32-bit EL0

#endif

END(vectors)