Loading arch/arm/boot/dts/qcom/msm8937-cdp.dtsi +58 −0 Original line number Diff line number Diff line Loading @@ -97,6 +97,64 @@ status = "ok"; }; &sdhc_1 { /* device core power supply */ vdd-supply = <&pm8937_l8>; qcom,vdd-voltage-level = <2900000 2900000>; qcom,vdd-current-level = <200 570000>; /* device communication power supply */ vdd-io-supply = <&pm8937_l5>; qcom,vdd-io-always-on; qcom,vdd-io-lpm-sup; qcom,vdd-io-voltage-level = <1800000 1800000>; qcom,vdd-io-current-level = <200 325000>; pinctrl-names = "active", "sleep"; pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>; pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>; qcom,clk-rates = <400000 20000000 25000000 50000000 96000000 192000000>; qcom,nonremovable; qcom,bus-speed-mode = "HS200_1p8v", "DDR_1p8v"; status = "ok"; }; &sdhc_2 { /* device core power supply */ vdd-supply = <&pm8937_l11>; qcom,vdd-voltage-level = <2950000 2950000>; qcom,vdd-current-level = <15000 800000>; /* device communication power supply */ vdd-io-supply = <&pm8937_l12>; qcom,vdd-io-voltage-level = <2950000 2950000>; qcom,vdd-io-current-level = <200 22000>; pinctrl-names = "active", "sleep"; pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; #address-cells = <0>; interrupt-parent = <&sdhc_2>; interrupts = <0 1 2>; #interrupt-cells = <1>; interrupt-map-mask = <0xffffffff>; interrupt-map = <0 &intc 0 125 0 1 &intc 0 221 0 2 &tlmm 67 0>; interrupt-names = "hc_irq", "pwr_irq", "status_irq"; cd-gpios = <&tlmm 67 0x1>; qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 200000000>; qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104"; status = "ok"; }; &spi_3 { /* BLSP1 QUP3 */ status = "ok"; maxim_sti@0 { Loading arch/arm/boot/dts/qcom/msm8937-mtp.dtsi +57 −0 Original line number Diff line number Diff line Loading @@ -85,3 +85,60 @@ pinctrl-2 = <&ts_release>; }; }; &sdhc_1 { /* device core power supply */ vdd-supply = <&pm8937_l8>; qcom,vdd-voltage-level = <2900000 2900000>; qcom,vdd-current-level = <200 570000>; /* device communication power supply */ vdd-io-supply = <&pm8937_l5>; qcom,vdd-io-always-on; qcom,vdd-io-lpm-sup; qcom,vdd-io-voltage-level = <1800000 1800000>; qcom,vdd-io-current-level = <200 325000>; pinctrl-names = "active", "sleep"; pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>; pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>; qcom,clk-rates = <400000 20000000 25000000 50000000 96000000 192000000>; qcom,nonremovable; qcom,bus-speed-mode = "HS200_1p8v", "DDR_1p8v"; status = "ok"; }; &sdhc_2 { /* device core power supply */ vdd-supply = <&pm8937_l11>; qcom,vdd-voltage-level = <2950000 2950000>; qcom,vdd-current-level = <15000 800000>; /* device communication power supply */ vdd-io-supply = <&pm8937_l12>; qcom,vdd-io-voltage-level = <2950000 2950000>; qcom,vdd-io-current-level = <200 22000>; pinctrl-names = "active", "sleep"; pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; #address-cells = <0>; interrupt-parent = <&sdhc_2>; interrupts = <0 1 2>; #interrupt-cells = <1>; interrupt-map-mask = <0xffffffff>; interrupt-map = <0 &intc 0 125 0 1 &intc 0 221 0 2 &tlmm 67 0>; interrupt-names = "hc_irq", "pwr_irq", "status_irq"; cd-gpios = <&tlmm 67 0x1>; qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 200000000>; qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104"; status = "ok"; }; arch/arm/boot/dts/qcom/msm8937-pinctrl.dtsi +152 −0 Original line number Diff line number Diff line Loading @@ -391,5 +391,157 @@ }; }; }; pmx_sdc1_rclk { sdc1_rclk_on: sdc1_rclk_on { config { pins = "sdc1_rclk"; bias-pull-down; /* pull down */ }; }; sdc1_rclk_off: sdc1_rclk_off { config { pins = "sdc1_rclk"; bias-pull-down; /* pull down */ }; }; }; pmx_sdc1_clk { sdc1_clk_on: sdc1_clk_on { config { pins = "sdc1_clk"; bias-disable; /* NO pull */ drive-strength = <16>; /* 16 MA */ }; }; sdc1_clk_off: sdc1_clk_off { config { pins = "sdc1_clk"; bias-disable; /* NO pull */ drive-strength = <2>; /* 2 MA */ }; }; }; pmx_sdc1_cmd { sdc1_cmd_on: sdc1_cmd_on { config { pins = "sdc1_cmd"; bias-pull-up; /* pull up */ drive-strength = <10>; /* 10 MA */ }; }; sdc1_cmd_off: sdc1_cmd_off { config { pins = "sdc1_cmd"; bias-pull-up; /* pull up */ drive-strength = <2>; /* 2 MA */ }; }; }; pmx_sdc1_data { sdc1_data_on: sdc1_data_on { config { pins = "sdc1_data"; bias-pull-up; /* pull up */ drive-strength = <10>; /* 10 MA */ }; }; sdc1_data_off: sdc1_data_off { config { pins = "sdc1_data"; bias-pull-up; /* pull up */ drive-strength = <2>; /* 2 MA */ }; }; }; sdhc2_cd_pin { sdc2_cd_on: cd_on { mux { pins = "gpio67"; function = "gpio"; }; config { pins = "gpio67"; drive-strength = <2>; bias-pull-up; }; }; sdc2_cd_off: cd_off { mux { pins = "gpio67"; function = "gpio"; }; config { pins = "gpio67"; drive-strength = <2>; bias-disable; }; }; }; pmx_sdc2_clk { sdc2_clk_on: sdc2_clk_on { config { pins = "sdc2_clk"; drive-strength = <16>; /* 16 MA */ bias-disable; /* NO pull */ }; }; sdc2_clk_off: sdc2_clk_off { config { pins = "sdc2_clk"; bias-disable; /* NO pull */ drive-strength = <2>; /* 2 MA */ }; }; }; pmx_sdc2_cmd { sdc2_cmd_on: sdc2_cmd_on { config { pins = "sdc2_cmd"; bias-pull-up; /* pull up */ drive-strength = <16>; /* 16 MA */ }; }; sdc2_cmd_off: sdc2_cmd_off { config { pins = "sdc2_cmd"; bias-pull-up; /* pull up */ drive-strength = <2>; /* 2 MA */ }; }; }; pmx_sdc2_data { sdc2_data_on: sdc2_data_on { config { pins = "sdc2_data"; bias-pull-up; /* pull up */ drive-strength = <16>; /* 16 MA */ }; }; sdc2_data_off: sdc2_data_off { config { pins = "sdc2_data"; bias-pull-up; /* pull up */ drive-strength = <2>; /* 2 MA */ }; }; }; }; }; arch/arm/boot/dts/qcom/msm8937-rumi.dts +54 −0 Original line number Diff line number Diff line Loading @@ -33,10 +33,64 @@ }; }; &sdhc_2 { /* device core power supply */ vdd-supply = <&pm8937_l11>; qcom,vdd-voltage-level = <2950000 2950000>; qcom,vdd-current-level = <15000 800000>; /* device communication power supply */ vdd-io-supply = <&pm8937_l12>; qcom,vdd-io-voltage-level = <2950000 2950000>; qcom,vdd-io-current-level = <200 22000>; pinctrl-names = "active", "sleep"; pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; #address-cells = <0>; interrupt-parent = <&sdhc_2>; interrupts = <0 1 2>; #interrupt-cells = <1>; interrupt-map-mask = <0xffffffff>; interrupt-map = <0 &intc 0 125 0 1 &intc 0 221 0 2 &tlmm 67 0>; interrupt-names = "hc_irq", "pwr_irq", "status_irq"; cd-gpios = <&tlmm 67 0x1>; qcom,clk-rates = <400000 25000000 50000000>; status = "ok"; }; &blsp1_uart2 { status = "ok"; }; &sdhc_1 { /* device core power supply */ vdd-supply = <&pm8937_l8>; qcom,vdd-voltage-level = <2900000 2900000>; qcom,vdd-current-level = <200 570000>; /* device communication power supply */ vdd-io-supply = <&pm8937_l5>; qcom,vdd-io-always-on; qcom,vdd-io-lpm-sup; qcom,vdd-io-voltage-level = <1800000 1800000>; qcom,vdd-io-current-level = <200 325000>; pinctrl-names = "active", "sleep"; pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>; pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>; qcom,nonremovable; qcom,clk-rates = <400000 25000000 50000000>; status = "ok"; }; &usb_otg { qcom,hsusb-otg-otg-control = <1>; qcom,emulation; Loading arch/arm/boot/dts/qcom/msm8937.dtsi +67 −0 Original line number Diff line number Diff line Loading @@ -94,6 +94,8 @@ i2c2 = &i2c_2; i2c5 = &i2c_5; spi3 = &spi_3; sdhc1 = &sdhc_1; /* SDC1 eMMC slot */ sdhc2 = &sdhc_2; /* SDC2 for SD card */ }; soc: soc { }; Loading Loading @@ -1396,6 +1398,71 @@ qcom,fast-shutdown; }; sdhc_1: sdhci@7824900 { compatible = "qcom,sdhci-msm"; reg = <0x7824900 0x500>, <0x7824000 0x800>; reg-names = "hc_mem", "core_mem"; interrupts = <0 123 0>, <0 138 0>; interrupt-names = "hc_irq", "pwr_irq"; qcom,bus-width = <8>; qcom,devfreq,freq-table = <52000000 200000000>; qcom,msm-bus,name = "sdhc1"; qcom,msm-bus,num-cases = <9>; qcom,msm-bus,num-paths = <1>; qcom,msm-bus,vectors-KBps = <78 512 0 0>, /* No vote */ <78 512 1046 3200>, /* 400 KB/s*/ <78 512 52286 160000>, /* 20 MB/s */ <78 512 65360 200000>, /* 25 MB/s */ <78 512 130718 400000>, /* 50 MB/s */ <78 512 130718 400000>, /* 100 MB/s */ <78 512 261438 800000>, /* 200 MB/s */ <78 512 261438 800000>, /* 400 MB/s */ <78 512 1338562 4096000>; /* Max. bandwidth */ qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000 100000000 200000000 400000000 4294967295>; clocks = <&clock_gcc clk_gcc_sdcc1_ahb_clk>, <&clock_gcc clk_gcc_sdcc1_apps_clk>; clock-names = "iface_clk", "core_clk"; status = "disabled"; }; sdhc_2: sdhci@7864900 { compatible = "qcom,sdhci-msm"; reg = <0x7864900 0x500>, <0x7864000 0x800>; reg-names = "hc_mem", "core_mem"; interrupts = <0 125 0>, <0 221 0>; interrupt-names = "hc_irq", "pwr_irq"; qcom,bus-width = <4>; qcom,msm-bus,name = "sdhc2"; qcom,msm-bus,num-cases = <8>; qcom,msm-bus,num-paths = <1>; qcom,msm-bus,vectors-KBps = <81 512 0 0>, /* No vote */ <81 512 1046 3200>, /* 400 KB/s*/ <81 512 52286 160000>, /* 20 MB/s */ <81 512 65360 200000>, /* 25 MB/s */ <81 512 130718 400000>, /* 50 MB/s */ <81 512 261438 800000>, /* 100 MB/s */ <81 512 261438 800000>, /* 200 MB/s */ <81 512 1338562 4096000>; /* Max. bandwidth */ qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000 100000000 200000000 400000000 4294967295>; clocks = <&clock_gcc clk_gcc_sdcc2_ahb_clk>, <&clock_gcc clk_gcc_sdcc2_apps_clk>; clock-names = "iface_clk", "core_clk"; status = "disabled"; }; spmi_bus: qcom,spmi@200f000 { compatible = "qcom,spmi-pmic-arb"; reg = <0x200f000 0x1000>, Loading Loading
arch/arm/boot/dts/qcom/msm8937-cdp.dtsi +58 −0 Original line number Diff line number Diff line Loading @@ -97,6 +97,64 @@ status = "ok"; }; &sdhc_1 { /* device core power supply */ vdd-supply = <&pm8937_l8>; qcom,vdd-voltage-level = <2900000 2900000>; qcom,vdd-current-level = <200 570000>; /* device communication power supply */ vdd-io-supply = <&pm8937_l5>; qcom,vdd-io-always-on; qcom,vdd-io-lpm-sup; qcom,vdd-io-voltage-level = <1800000 1800000>; qcom,vdd-io-current-level = <200 325000>; pinctrl-names = "active", "sleep"; pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>; pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>; qcom,clk-rates = <400000 20000000 25000000 50000000 96000000 192000000>; qcom,nonremovable; qcom,bus-speed-mode = "HS200_1p8v", "DDR_1p8v"; status = "ok"; }; &sdhc_2 { /* device core power supply */ vdd-supply = <&pm8937_l11>; qcom,vdd-voltage-level = <2950000 2950000>; qcom,vdd-current-level = <15000 800000>; /* device communication power supply */ vdd-io-supply = <&pm8937_l12>; qcom,vdd-io-voltage-level = <2950000 2950000>; qcom,vdd-io-current-level = <200 22000>; pinctrl-names = "active", "sleep"; pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; #address-cells = <0>; interrupt-parent = <&sdhc_2>; interrupts = <0 1 2>; #interrupt-cells = <1>; interrupt-map-mask = <0xffffffff>; interrupt-map = <0 &intc 0 125 0 1 &intc 0 221 0 2 &tlmm 67 0>; interrupt-names = "hc_irq", "pwr_irq", "status_irq"; cd-gpios = <&tlmm 67 0x1>; qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 200000000>; qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104"; status = "ok"; }; &spi_3 { /* BLSP1 QUP3 */ status = "ok"; maxim_sti@0 { Loading
arch/arm/boot/dts/qcom/msm8937-mtp.dtsi +57 −0 Original line number Diff line number Diff line Loading @@ -85,3 +85,60 @@ pinctrl-2 = <&ts_release>; }; }; &sdhc_1 { /* device core power supply */ vdd-supply = <&pm8937_l8>; qcom,vdd-voltage-level = <2900000 2900000>; qcom,vdd-current-level = <200 570000>; /* device communication power supply */ vdd-io-supply = <&pm8937_l5>; qcom,vdd-io-always-on; qcom,vdd-io-lpm-sup; qcom,vdd-io-voltage-level = <1800000 1800000>; qcom,vdd-io-current-level = <200 325000>; pinctrl-names = "active", "sleep"; pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>; pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>; qcom,clk-rates = <400000 20000000 25000000 50000000 96000000 192000000>; qcom,nonremovable; qcom,bus-speed-mode = "HS200_1p8v", "DDR_1p8v"; status = "ok"; }; &sdhc_2 { /* device core power supply */ vdd-supply = <&pm8937_l11>; qcom,vdd-voltage-level = <2950000 2950000>; qcom,vdd-current-level = <15000 800000>; /* device communication power supply */ vdd-io-supply = <&pm8937_l12>; qcom,vdd-io-voltage-level = <2950000 2950000>; qcom,vdd-io-current-level = <200 22000>; pinctrl-names = "active", "sleep"; pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; #address-cells = <0>; interrupt-parent = <&sdhc_2>; interrupts = <0 1 2>; #interrupt-cells = <1>; interrupt-map-mask = <0xffffffff>; interrupt-map = <0 &intc 0 125 0 1 &intc 0 221 0 2 &tlmm 67 0>; interrupt-names = "hc_irq", "pwr_irq", "status_irq"; cd-gpios = <&tlmm 67 0x1>; qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 200000000>; qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104"; status = "ok"; };
arch/arm/boot/dts/qcom/msm8937-pinctrl.dtsi +152 −0 Original line number Diff line number Diff line Loading @@ -391,5 +391,157 @@ }; }; }; pmx_sdc1_rclk { sdc1_rclk_on: sdc1_rclk_on { config { pins = "sdc1_rclk"; bias-pull-down; /* pull down */ }; }; sdc1_rclk_off: sdc1_rclk_off { config { pins = "sdc1_rclk"; bias-pull-down; /* pull down */ }; }; }; pmx_sdc1_clk { sdc1_clk_on: sdc1_clk_on { config { pins = "sdc1_clk"; bias-disable; /* NO pull */ drive-strength = <16>; /* 16 MA */ }; }; sdc1_clk_off: sdc1_clk_off { config { pins = "sdc1_clk"; bias-disable; /* NO pull */ drive-strength = <2>; /* 2 MA */ }; }; }; pmx_sdc1_cmd { sdc1_cmd_on: sdc1_cmd_on { config { pins = "sdc1_cmd"; bias-pull-up; /* pull up */ drive-strength = <10>; /* 10 MA */ }; }; sdc1_cmd_off: sdc1_cmd_off { config { pins = "sdc1_cmd"; bias-pull-up; /* pull up */ drive-strength = <2>; /* 2 MA */ }; }; }; pmx_sdc1_data { sdc1_data_on: sdc1_data_on { config { pins = "sdc1_data"; bias-pull-up; /* pull up */ drive-strength = <10>; /* 10 MA */ }; }; sdc1_data_off: sdc1_data_off { config { pins = "sdc1_data"; bias-pull-up; /* pull up */ drive-strength = <2>; /* 2 MA */ }; }; }; sdhc2_cd_pin { sdc2_cd_on: cd_on { mux { pins = "gpio67"; function = "gpio"; }; config { pins = "gpio67"; drive-strength = <2>; bias-pull-up; }; }; sdc2_cd_off: cd_off { mux { pins = "gpio67"; function = "gpio"; }; config { pins = "gpio67"; drive-strength = <2>; bias-disable; }; }; }; pmx_sdc2_clk { sdc2_clk_on: sdc2_clk_on { config { pins = "sdc2_clk"; drive-strength = <16>; /* 16 MA */ bias-disable; /* NO pull */ }; }; sdc2_clk_off: sdc2_clk_off { config { pins = "sdc2_clk"; bias-disable; /* NO pull */ drive-strength = <2>; /* 2 MA */ }; }; }; pmx_sdc2_cmd { sdc2_cmd_on: sdc2_cmd_on { config { pins = "sdc2_cmd"; bias-pull-up; /* pull up */ drive-strength = <16>; /* 16 MA */ }; }; sdc2_cmd_off: sdc2_cmd_off { config { pins = "sdc2_cmd"; bias-pull-up; /* pull up */ drive-strength = <2>; /* 2 MA */ }; }; }; pmx_sdc2_data { sdc2_data_on: sdc2_data_on { config { pins = "sdc2_data"; bias-pull-up; /* pull up */ drive-strength = <16>; /* 16 MA */ }; }; sdc2_data_off: sdc2_data_off { config { pins = "sdc2_data"; bias-pull-up; /* pull up */ drive-strength = <2>; /* 2 MA */ }; }; }; }; };
arch/arm/boot/dts/qcom/msm8937-rumi.dts +54 −0 Original line number Diff line number Diff line Loading @@ -33,10 +33,64 @@ }; }; &sdhc_2 { /* device core power supply */ vdd-supply = <&pm8937_l11>; qcom,vdd-voltage-level = <2950000 2950000>; qcom,vdd-current-level = <15000 800000>; /* device communication power supply */ vdd-io-supply = <&pm8937_l12>; qcom,vdd-io-voltage-level = <2950000 2950000>; qcom,vdd-io-current-level = <200 22000>; pinctrl-names = "active", "sleep"; pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; #address-cells = <0>; interrupt-parent = <&sdhc_2>; interrupts = <0 1 2>; #interrupt-cells = <1>; interrupt-map-mask = <0xffffffff>; interrupt-map = <0 &intc 0 125 0 1 &intc 0 221 0 2 &tlmm 67 0>; interrupt-names = "hc_irq", "pwr_irq", "status_irq"; cd-gpios = <&tlmm 67 0x1>; qcom,clk-rates = <400000 25000000 50000000>; status = "ok"; }; &blsp1_uart2 { status = "ok"; }; &sdhc_1 { /* device core power supply */ vdd-supply = <&pm8937_l8>; qcom,vdd-voltage-level = <2900000 2900000>; qcom,vdd-current-level = <200 570000>; /* device communication power supply */ vdd-io-supply = <&pm8937_l5>; qcom,vdd-io-always-on; qcom,vdd-io-lpm-sup; qcom,vdd-io-voltage-level = <1800000 1800000>; qcom,vdd-io-current-level = <200 325000>; pinctrl-names = "active", "sleep"; pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>; pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>; qcom,nonremovable; qcom,clk-rates = <400000 25000000 50000000>; status = "ok"; }; &usb_otg { qcom,hsusb-otg-otg-control = <1>; qcom,emulation; Loading
arch/arm/boot/dts/qcom/msm8937.dtsi +67 −0 Original line number Diff line number Diff line Loading @@ -94,6 +94,8 @@ i2c2 = &i2c_2; i2c5 = &i2c_5; spi3 = &spi_3; sdhc1 = &sdhc_1; /* SDC1 eMMC slot */ sdhc2 = &sdhc_2; /* SDC2 for SD card */ }; soc: soc { }; Loading Loading @@ -1396,6 +1398,71 @@ qcom,fast-shutdown; }; sdhc_1: sdhci@7824900 { compatible = "qcom,sdhci-msm"; reg = <0x7824900 0x500>, <0x7824000 0x800>; reg-names = "hc_mem", "core_mem"; interrupts = <0 123 0>, <0 138 0>; interrupt-names = "hc_irq", "pwr_irq"; qcom,bus-width = <8>; qcom,devfreq,freq-table = <52000000 200000000>; qcom,msm-bus,name = "sdhc1"; qcom,msm-bus,num-cases = <9>; qcom,msm-bus,num-paths = <1>; qcom,msm-bus,vectors-KBps = <78 512 0 0>, /* No vote */ <78 512 1046 3200>, /* 400 KB/s*/ <78 512 52286 160000>, /* 20 MB/s */ <78 512 65360 200000>, /* 25 MB/s */ <78 512 130718 400000>, /* 50 MB/s */ <78 512 130718 400000>, /* 100 MB/s */ <78 512 261438 800000>, /* 200 MB/s */ <78 512 261438 800000>, /* 400 MB/s */ <78 512 1338562 4096000>; /* Max. bandwidth */ qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000 100000000 200000000 400000000 4294967295>; clocks = <&clock_gcc clk_gcc_sdcc1_ahb_clk>, <&clock_gcc clk_gcc_sdcc1_apps_clk>; clock-names = "iface_clk", "core_clk"; status = "disabled"; }; sdhc_2: sdhci@7864900 { compatible = "qcom,sdhci-msm"; reg = <0x7864900 0x500>, <0x7864000 0x800>; reg-names = "hc_mem", "core_mem"; interrupts = <0 125 0>, <0 221 0>; interrupt-names = "hc_irq", "pwr_irq"; qcom,bus-width = <4>; qcom,msm-bus,name = "sdhc2"; qcom,msm-bus,num-cases = <8>; qcom,msm-bus,num-paths = <1>; qcom,msm-bus,vectors-KBps = <81 512 0 0>, /* No vote */ <81 512 1046 3200>, /* 400 KB/s*/ <81 512 52286 160000>, /* 20 MB/s */ <81 512 65360 200000>, /* 25 MB/s */ <81 512 130718 400000>, /* 50 MB/s */ <81 512 261438 800000>, /* 100 MB/s */ <81 512 261438 800000>, /* 200 MB/s */ <81 512 1338562 4096000>; /* Max. bandwidth */ qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000 100000000 200000000 400000000 4294967295>; clocks = <&clock_gcc clk_gcc_sdcc2_ahb_clk>, <&clock_gcc clk_gcc_sdcc2_apps_clk>; clock-names = "iface_clk", "core_clk"; status = "disabled"; }; spmi_bus: qcom,spmi@200f000 { compatible = "qcom,spmi-pmic-arb"; reg = <0x200f000 0x1000>, Loading