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Commit 6f4fb9da authored by Harsh Shah's avatar Harsh Shah
Browse files

msm: camera: isp: Update Slave frame_id based on Master



In master-slave mode, set Slave frame id = master frame id,
if the delta between the timestamp is < Threshold. If delta is
higher than threshold, slave frame_id = master + 1.

Change-Id: I68f1c5354334bc11795739836a9a75436bde38be
Signed-off-by: default avatarHarsh Shah <harshs@codeaurora.org>
parent a36fe9d5
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+1 −0
Original line number Diff line number Diff line
@@ -603,6 +603,7 @@ struct msm_vfe_common_dev_data {
	enum msm_vfe_dual_hw_type dual_hw_type;
	struct msm_vfe_sof_info master_sof_info;
	uint8_t master_active;
	uint32_t sof_delta_threshold; /* Updated by Master */
	uint32_t num_slave;
	uint32_t reserved_slave_mask;
	uint32_t slave_active_mask;
+6 −6
Original line number Diff line number Diff line
@@ -450,11 +450,10 @@ static void msm_vfe40_process_input_irq(struct vfe_device *vfe_dev,
	if (!(irq_status0 & 0x1000003))
		return;

	if (irq_status0 & 0x1)
		vfe_dev->axi_data.src_info[VFE_PIX_0].camif_sof_frame_id++;

	if (vfe_dev->axi_data.src_info[VFE_PIX_0].camif_sof_frame_id == 0)
		vfe_dev->axi_data.src_info[VFE_PIX_0].camif_sof_frame_id = 1;
	if (irq_status0 & (1 << 0)) {
		ISP_DBG("%s: SOF IRQ\n", __func__);
		msm_isp_increment_frame_id(vfe_dev, VFE_PIX_0, ts);
	}

	if (irq_status0 & (1 << 24)) {
		ISP_DBG("%s: Fetch Engine Read IRQ\n", __func__);
@@ -671,7 +670,7 @@ static void msm_vfe40_process_reg_update(struct vfe_device *vfe_dev,
	for (i = VFE_PIX_0; i <= VFE_RAW_2; i++) {
		if (shift_irq & BIT(i)) {
			reg_updated |= BIT(i);
			ISP_DBG("%s update_mask %x\n", __func__,
			ISP_DBG("%s REG_UPDATE IRQ %x\n", __func__,
				(uint32_t)BIT(i));
			switch (i) {
			case VFE_PIX_0:
@@ -685,6 +684,7 @@ static void msm_vfe40_process_reg_update(struct vfe_device *vfe_dev,
			case VFE_RAW_0:
			case VFE_RAW_1:
			case VFE_RAW_2:
				msm_isp_increment_frame_id(vfe_dev, i, ts);
				msm_isp_notify(vfe_dev, ISP_EVENT_SOF, i, ts);
				msm_isp_update_framedrop_reg(vfe_dev, i);
				/*
+6 −6
Original line number Diff line number Diff line
@@ -294,11 +294,10 @@ static void msm_vfe44_process_input_irq(struct vfe_device *vfe_dev,
	if (!(irq_status0 & 0x1000003))
		return;

	if (irq_status0 & 0x1)
		vfe_dev->axi_data.src_info[VFE_PIX_0].camif_sof_frame_id++;

	if (vfe_dev->axi_data.src_info[VFE_PIX_0].camif_sof_frame_id == 0)
		vfe_dev->axi_data.src_info[VFE_PIX_0].camif_sof_frame_id = 1;
	if (irq_status0 & (1 << 0)) {
		ISP_DBG("%s: SOF IRQ\n", __func__);
		msm_isp_increment_frame_id(vfe_dev, VFE_PIX_0, ts);
	}

	if (irq_status0 & (1 << 24)) {
		ISP_DBG("%s: Fetch Engine Read IRQ\n", __func__);
@@ -515,7 +514,7 @@ static void msm_vfe44_process_reg_update(struct vfe_device *vfe_dev,
	for (i = VFE_PIX_0; i <= VFE_RAW_2; i++) {
		if (shift_irq & BIT(i)) {
			reg_updated |= BIT(i);
			ISP_DBG("%s update_mask %x\n", __func__,
			ISP_DBG("%s REG_UPDATE IRQ %x\n", __func__,
				(uint32_t)BIT(i));
			switch (i) {
			case VFE_PIX_0:
@@ -529,6 +528,7 @@ static void msm_vfe44_process_reg_update(struct vfe_device *vfe_dev,
			case VFE_RAW_0:
			case VFE_RAW_1:
			case VFE_RAW_2:
				msm_isp_increment_frame_id(vfe_dev, i, ts);
				msm_isp_notify(vfe_dev, ISP_EVENT_SOF, i, ts);
				msm_isp_update_framedrop_reg(vfe_dev, i);
				/*
+7 −7
Original line number Diff line number Diff line
@@ -321,18 +321,16 @@ static void msm_vfe46_process_input_irq(struct vfe_device *vfe_dev,
	if (!(irq_status0 & 0x1000003))
		return;

	if (irq_status0 & 0x1)
		vfe_dev->axi_data.src_info[VFE_PIX_0].camif_sof_frame_id++;

	if (vfe_dev->axi_data.src_info[VFE_PIX_0].camif_sof_frame_id == 0)
		vfe_dev->axi_data.src_info[VFE_PIX_0].camif_sof_frame_id = 1;

	if (irq_status0 & (1 << 24)) {
		ISP_DBG("%s: Fetch Engine Read IRQ\n", __func__);
		msm_isp_fetch_engine_done_notify(vfe_dev,
			&vfe_dev->fetch_engine_info);
	}

	if (irq_status0 & (1 << 0)) {
		ISP_DBG("%s: SOF IRQ\n", __func__);
		msm_isp_increment_frame_id(vfe_dev, VFE_PIX_0, ts);
	}

	if (irq_status0 & (1 << 1))
		ISP_DBG("%s: EOF IRQ\n", __func__);
@@ -445,8 +443,9 @@ static void msm_vfe46_process_reg_update(struct vfe_device *vfe_dev,
	for (i = VFE_PIX_0; i <= VFE_RAW_2; i++) {
		if (shift_irq & BIT(i)) {
			reg_updated |= BIT(i);
			ISP_DBG("%s update_mask %x\n", __func__,
			ISP_DBG("%s Reg Update IRQ %x\n", __func__,
				(uint32_t)BIT(i));

			switch (i) {
			case VFE_PIX_0:
				msm_isp_save_framedrop_values(vfe_dev);
@@ -459,6 +458,7 @@ static void msm_vfe46_process_reg_update(struct vfe_device *vfe_dev,
			case VFE_RAW_0:
			case VFE_RAW_1:
			case VFE_RAW_2:
				msm_isp_increment_frame_id(vfe_dev, i, ts);
				msm_isp_notify(vfe_dev, ISP_EVENT_SOF, i, ts);
				msm_isp_update_framedrop_reg(vfe_dev, i);
				/*
+6 −6
Original line number Diff line number Diff line
@@ -436,11 +436,10 @@ static void msm_vfe47_process_input_irq(struct vfe_device *vfe_dev,
	if (!(irq_status0 & 0x1000003))
		return;

	if (irq_status0 & 0x1)
		vfe_dev->axi_data.src_info[VFE_PIX_0].camif_sof_frame_id++;

	if (vfe_dev->axi_data.src_info[VFE_PIX_0].camif_sof_frame_id == 0)
		vfe_dev->axi_data.src_info[VFE_PIX_0].camif_sof_frame_id = 1;
	if (irq_status0 & (1 << 0)) {
		ISP_DBG("%s: SOF IRQ\n", __func__);
		msm_isp_increment_frame_id(vfe_dev, VFE_PIX_0, ts);
	}

	if (irq_status0 & (1 << 24)) {
		ISP_DBG("%s: Fetch Engine Read IRQ\n", __func__);
@@ -562,7 +561,7 @@ static void msm_vfe47_process_reg_update(struct vfe_device *vfe_dev,
	for (i = VFE_PIX_0; i <= VFE_RAW_2; i++) {
		if (shift_irq & BIT(i)) {
			reg_updated |= BIT(i);
			ISP_DBG("%s update_mask %x\n", __func__,
			ISP_DBG("%s REG_UPDATE IRQ %x\n", __func__,
				(uint32_t)BIT(i));
			switch (i) {
			case VFE_PIX_0:
@@ -576,6 +575,7 @@ static void msm_vfe47_process_reg_update(struct vfe_device *vfe_dev,
			case VFE_RAW_0:
			case VFE_RAW_1:
			case VFE_RAW_2:
				msm_isp_increment_frame_id(vfe_dev, i, ts);
				msm_isp_notify(vfe_dev, ISP_EVENT_SOF, i, ts);
				msm_isp_update_framedrop_reg(vfe_dev, i);
				/*
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