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Commit 6eef27b6 authored by Christian König's avatar Christian König Committed by Sasha Levin
Browse files

drm/radeon: drop setting UPLL to sleep mode 

[ Upstream commit a17d4996e051e78d164989b894608cf37cd5110b ]

Just keep it working, seems to fix some PLL problems.

Bug: https://bugs.freedesktop.org/show_bug.cgi?id=73378



Signed-off-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Signed-off-by: default avatarSasha Levin <sasha.levin@oracle.com>
parent 570f8c77

drivers/gpu/drm/radeon/si.c

+2 −4
Original line number Diff line number Diff line
@@ -7115,8 +7115,7 @@ int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk) 
	WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK);



	if (!vclk || !dclk) {

		/* keep the Bypass mode, put PLL to sleep */

		WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK);

		/* keep the Bypass mode */

		return 0;

	}
@@ -7132,8 +7131,7 @@ int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk) 
	/* set VCO_MODE to 1 */

	WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_VCO_MODE_MASK, ~UPLL_VCO_MODE_MASK);



	/* toggle UPLL_SLEEP to 1 then back to 0 */

	WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK);

	/* disable sleep mode */

	WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_SLEEP_MASK);



	/* deassert UPLL_RESET */