Merge "msm: kgsl: Clean up IOMMU context bank configuration"

Required properties:

- compatible : one of:

	- "qcom,kgsl-smmu-v1"

	- "qcom,kgsl-smmu-v2"

- reg		: Base address and size of the SMMU.

- num_cb	: Number of context banks

- clocks	: List of clocks to be used during SMMU register access. See

		  Documentation/devicetree/bindings/clock/clock-bindings.txt

		  for information about the format. For each clock specified

		  the "clocks" property (above). See

		  Documentation/devicetree/bindings/clock/clock-bindings.txt

		  for more info.

- qcom,protect  : The GPU register region which must be protected by a CP

		  protected mode. On some targets this region must cover

		  the entire SMMU register space, on others there

		  is a separate aperture for CP to program context banks.

Optional properties:

- qcom,micro-mmu-control : Some targets provide an implementation defined

		  register for blocking translation requests during GPU side

		  programming.  This property specifies the offset of this

		  register within the iommu register space.

- qcom,retention :  A boolean specifying if retention is supported on this target

- qcom,global_pt :  A boolean specifying if global pagetable should be used.

		  When not set we use per process pagetables

- qcom,hyp_secure_alloc : A bool specifying if the hypervisor is used on this target

		  for secure buffer allocation

- qcom,secure_align_mask: A mask for determining how secure buffers need to

		  be aligned

- qcom,coherent-htw: A boolean specifying if coherent hardware table walks should

		  be enabled.

- List of sub nodes, one for each of the translation context banks supported.

  The driver uses the names of these nodes to determine how they are used,

  currently supported names are:

  - gfx3d_user : Used for the 'normal' GPU address space.

  - gfx3d_secure : Used for the content protection address space.

  Each sub node has the following required properties:

	- compatible : "qcom,smmu-kgsl-cb"

	- label : Name of the context bank

	- iommus : Specifies the SID's used by this context bank, this needs to be

		   <kgsl_smmu SID> pair, kgsl_smmu is the string parsed by iommu

		   driver to match this context bank with the kgsl_smmu device

		   defined in iommu device tree.

	 - retention :  A boolean specifying if retention is supported on this

			target

	 - qcom,global_pt :  A boolean specifying if global pagetable should be used.

			     When not set we use per process pagetables

	 - qcom,hyp_secure_alloc : A bool specifying if the hypervisor is used on

				   this target for secure buffer allocation

	 - qcom,secure_align_mask: A mask for determining how secure buffers need to

				   be aligned

		   defined in iommu device tree. On targets where the msm iommu

		   driver is used rather than the arm smmu driver, this property

		   may be absent.

	- qcom,gpu-offset :  Offset into the GPU register space for accessing

		   this context bank. On some targets the iommu registers are not

		   part of the GPU's register space, and a separate register aperture

		   is used. Otherwise the same register offsets may be used for CPU

		   or GPU side programming.

Example:

	msm_iommu: qcom,kgsl-iommu {

		compatible = "qcom,kgsl-smmu-v2";

		reg = <0xb40000 0x20000>;

		qcom,protect = <0x40000 0x20000>;

		clocks = <&clock_mmss clk_gpu_ahb_clk>,

			<&clock_gcc clk_gcc_mmss_bimc_gfx_clk>,

			<&clock_mmss clk_mmss_mmagic_ahb_clk>,

			<&clock_mmss clk_mmss_mmagic_cfg_ahb_clk>;

		clock-names = "gpu_ahb_clk", "bimc_gfx_clk", "mmagic_ahb_clk", "mmagic_cfg_ahb_clk";

		num_cb = <2>;

		qcom,secure_align_mask = <0xfff>;

		retention;

		qcom,retention;

		qcom,global_pt;

		iommu_kgsl_cb2: iommu_kgsl_cb2 {

		gfx3d_user: gfx3d_user {

			compatible = "qcom,smmu-kgsl-cb";

			label = "gfx3d_user";

			iommus = <&kgsl_smmu 0>,

				 <&kgsl_smmu 1>;

			qcom,gpu-offset = <0x48000>;

		};

		iommu_kgsl_cb3: iommu_kgsl_cb3 {

		gfx3d_secure: gfx3d_secure {

			compatible = "qcom,smmu-kgsl-cb";

			label = "gfx3d_secure";

			iommus = <&kgsl_smmu 2>;

		};

	};

                  support, the stream matching table is programmed before

                  control is even turned over to Linux.

- qcom,dynamic  : Allow dynamic domains to be attached. This is only

		  useful if the upstream hardware is capable of switching

		  between multiple domains within a single context bank.

- clocks        : List of clocks to be used during SMMU register access. See

                  Documentation/devicetree/bindings/clock/clock-bindings.txt

                  for information about the format. For each clock specified

		};

	};

	kgsl_msm_iommu: qcom,kgsl-iommu {

		compatible = "qcom,kgsl-smmu-v2";

		reg = <0x1f00000 0x10000>;

		/*

		* The gpu can only program a single context bank

		* at this fixed offset.

		*/

		qcom,protect = <0x48000 0x1000>;

		clocks = <&clock_gcc clk_gcc_smmu_cfg_clk>,

			<&clock_gcc clk_gcc_gfx_tcu_clk>,

			<&clock_gcc clk_gcc_gtcu_ahb_clk>,

			<&clock_gcc clk_gcc_gfx_tbu_clk>;

		clock-names = "iface_clk", "core_clk", "gtcu_iface_clk",

				"gtbu_clk";

		gfx3d_user: gfx3d_user {

			compatible = "qcom,smmu-kgsl-cb";

			qcom,gpu-offset = <0x48000>;

		};

	};

};

		clock-names = "iface_clk", "core_clk";

		status = "ok";

		gfx3d_user: qcom,iommu-ctx@1f08000 {

		qcom,iommu-ctx@1f08000 {

			compatible = "qcom,msm-smmu-v2-ctx";

			reg = <0x1f08000 0x1000>;

			interrupts = <0 240 0>;

			label = "gfx3d_user";

		};

		gfx3d_secure: qcom,iommu-ctx@1f09000 {

		qcom,iommu-ctx@1f09000 {

			compatible = "qcom,msm-smmu-v2-ctx";

			reg = <0x1f09000 0x1000>;

			qcom,secure-context;

			label = "gfx3d_secure";

		};

		gfx3d_priv: qcom,iommu-ctx@1f0b000 {

		qcom,iommu-ctx@1f0b000 {

			compatible = "qcom,msm-smmu-v2-ctx";

			reg = <0x1f0b000 0x1000>;

			interrupts = <0 245 0>;

	};

	/* IOMMU Data */

	kgsl_msm_iommu: qcom,kgsl-iommu {

		compatible = "qcom,kgsl-smmu-v2";

		reg = <0xb40000 0x20000>;

		qcom,protect = <0x40000 0x20000>;

		qcom,micro-mmu-control = <0x6000>;

		clocks = <&clock_mmss clk_mmss_mmagic_ahb_clk>,

			<&clock_mmss clk_mmss_mmagic_cfg_ahb_clk>,

			<&clock_gpu clk_gpu_ahb_clk>,

			<&clock_gcc clk_gcc_bimc_gfx_clk>;

		clock-names = "mmagic_ahb_clk", "mmagic_cfg_ahb_clk", "gpu_ahb_clk",

			"gcc_mmss_bimc_gfx_clk", "gcc_bimc_gfx_clk";

		num_cb = <2>;

		qcom,secure_align_mask = <0xfff>;

		retention;

		qcom,retention;

		iommu_kgsl_cb2: iommu_kgsl_cb2 {

		gfx3d_user: gfx3d_user {

			compatible = "qcom,smmu-kgsl-cb";

			label = "gfx3d_user";

			iommus = <&kgsl_smmu 0>;

			qcom,gpu-offset = <0x48000>;

		};

		iommu_kgsl_cb3: iommu_kgsl_cb3 {

		gfx3d_secure: gfx3d_secure {

			compatible = "qcom,smmu-kgsl-cb";

			label = "gfx3d_secure";

			iommus = <&kgsl_smmu 2>;

		};

	};

};