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Commit 6ec32400 authored by Lucas Stach's avatar Lucas Stach Committed by Olof Johansson
Browse files

clk: tegra: add ac97 controller clock 



AC97 controller clock is hardwired to pll_a_out0.

Signed-off-by: default avatarLucas Stach <dev@lynxeye.de>
Acked-by: default avatarPeter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-by: default avatarPrashant Gaikwad <pgaikwad@nvidia.com>
Acked-by: default avatarMike Turquette <mturquette@linaro.org>
Tested-by: default avatarStephen Warren <swarren@nvidia.com>
Signed-off-by: default avatarStephen Warren <swarren@nvidia.com>
Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parent 7e949844

drivers/clk/tegra/clk-tegra20.c

+8 −0
Original line number Diff line number Diff line
@@ -872,6 +872,14 @@ static void __init tegra20_periph_clk_init(void) 
	struct clk *clk;

	int i;



	/* ac97 */

	clk = tegra_clk_register_periph_gate("ac97", "pll_a_out0",

				    TEGRA_PERIPH_ON_APB,

				    clk_base, 0, 3, &periph_l_regs,

				    periph_clk_enb_refcnt);

	clk_register_clkdev(clk, NULL, "tegra20-ac97");

	clks[ac97] = clk;



	/* apbdma */

	clk = tegra_clk_register_periph_gate("apbdma", "pclk", 0, clk_base,

				    0, 34, &periph_h_regs,