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Commit 6ec08c71 authored by Sebastian Andrzej Siewior's avatar Sebastian Andrzej Siewior Committed by Dinh Nguyen
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ARM: dts: socfpga: add gpio pieces 



The cycloneV has three gpio controllers, each one with 29 gpios. This patch
adds the three controller with the gpio driver which is now sitting the
gpio tree.

Cc: devicetree@vger.kernel.org
Acked-by: default avatarAlan Tull <atull@altera.com>
Signed-off-by: default avatarSebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: default avatarDinh Nguyen <dinguyen@altera.com>
parent 8cb289ed

arch/arm/boot/dts/socfpga.dtsi

+60 −0
Original line number Diff line number Diff line
@@ -543,6 +543,66 @@ 
			status = "disabled";

		};



		gpio@ff708000 {

			#address-cells = <1>;

			#size-cells = <0>;

			compatible = "snps,dw-apb-gpio";

			reg = <0xff708000 0x1000>;

			clocks = <&per_base_clk>;

			status = "disabled";



			gpio0: gpio-controller@0 {

				compatible = "snps,dw-apb-gpio-port";

				gpio-controller;

				#gpio-cells = <2>;

				snps,nr-gpios = <29>;

				reg = <0>;

				interrupt-controller;

				#interrupt-cells = <2>;

				interrupts = <0 164 4>;

			};

		};



		gpio@ff709000 {

			#address-cells = <1>;

			#size-cells = <0>;

			compatible = "snps,dw-apb-gpio";

			reg = <0xff709000 0x1000>;

			clocks = <&per_base_clk>;

			status = "disabled";



			gpio1: gpio-controller@0 {

				compatible = "snps,dw-apb-gpio-port";

				gpio-controller;

				#gpio-cells = <2>;

				snps,nr-gpios = <29>;

				reg = <0>;

				interrupt-controller;

				#interrupt-cells = <2>;

				interrupts = <0 165 4>;

			};

		};



		gpio@ff70a000 {

			#address-cells = <1>;

			#size-cells = <0>;

			compatible = "snps,dw-apb-gpio";

			reg = <0xff70a000 0x1000>;

			clocks = <&per_base_clk>;

			status = "disabled";



			gpio2: gpio-controller@0 {

				compatible = "snps,dw-apb-gpio-port";

				gpio-controller;

				#gpio-cells = <2>;

				snps,nr-gpios = <27>;

				reg = <0>;

				interrupt-controller;

				#interrupt-cells = <2>;

				interrupts = <0 166 4>;

			};

		};



		L2: l2-cache@fffef000 {

			compatible = "arm,pl310-cache";

			reg = <0xfffef000 0x1000>;