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Commit 6ea889de authored by Jaydeep Sen's avatar Jaydeep Sen Committed by Gerrit - the friendly Code Review server
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clk: msm: 8937: Add support for spm pll management in msm8937 



Make the corresponding device tree changes for SPM child node to probe.
This is required for the spm event management to be handled for the SR2/HF
PLL of C0/C1. Also accommodate latest frequency plan changes for debug mux
values to measure clock frequency.

Change-Id: Ia5d68331407a6ecdcf85e230ade7aa3fd497c466
Signed-off-by: default avatarJaydeep Sen <jsen@codeaurora.org>
parent 72ee5cb1

Documentation/devicetree/bindings/arm/msm/clock-controller.txt

+1 −0
Original line number Diff line number Diff line
@@ -23,6 +23,7 @@ Required properties: 
			"qcom,gcc-8996-v2"

			"qcom,gcc-8996-v3"

			"qcom,gcc-8937"

			"qcom,gcc-spm-8937"

			"qcom,gcc-titanium"

			"qcom,rpmcc-8994"

			"qcom,rpmcc-8992"

arch/arm/boot/dts/qcom/msm8937.dtsi

+9 −1
Original line number Diff line number Diff line
@@ -357,6 +357,13 @@ 
		vdd_hf_dig-supply = <&pm8937_s2_level_ao>;

		vdd_hf_pll-supply = <&pm8937_l7_ao>;

		#clock-cells = <1>;

		ranges;

		qcom,spm@0 {

			compatible = "qcom,gcc-spm-8937";

			reg = <0x0b111200 0x100>,

			      <0x0b011200 0x100>;

			reg-names = "spm_c0_base", "spm_c1_base";

		};

	};



	clock_debug: qcom,cc-debug@1874000 {
@@ -382,10 +389,11 @@ 
			 <&clock_gcc clk_a53ss_c0_pll>,

			 <&clock_gcc clk_gpll0_ao_clk_src>,

			 <&clock_gcc clk_a53ss_c1_pll>,

			 <&clock_gcc clk_gpll0_ao_clk_src>,

			 <&clock_gcc clk_gpll0_ao_clk_src>;

		clock-names = "clk-c0-4", "clk-c0-5",

				"clk-c1-4", "clk-c1-5",

				"clk-cci-4";

				"clk-cci-4", "clk-cci-2";

		qcom,speed0-bin-v0-c0 =

			<          0 0>,

			<  806400000 1>,

drivers/clk/msm/clock-gcc-8952.c

+24 −17
Original line number Diff line number Diff line
@@ -3561,6 +3561,7 @@ static struct mux_clk gcc_debug_mux_8937 = { 
		{ &gcc_camss_vfe1_clk.c, 0x01a1 },

		{ &gcc_camss_vfe1_ahb_clk.c, 0x01a2 },

		{ &gcc_camss_vfe1_axi_clk.c, 0x01a3 },

		{ &gcc_camss_cpp_axi_clk.c, 0x01a4 },

		{ &gcc_venus0_core0_vcodec0_clk.c, 0x01b8 },

		{ &gcc_camss_mclk2_clk.c, 0x01bd },

		{ &gcc_oxili_timer_clk.c, 0x01e9 },
@@ -3571,14 +3572,14 @@ static struct mux_clk gcc_debug_mux_8937 = { 
		{ &gcc_venus0_ahb_clk.c, 0x01f3 },

		{ &gcc_mdss_ahb_clk.c, 0x01f6 },

		{ &gcc_mdss_axi_clk.c, 0x01f7 },

		{ &gcc_mdss_pclk0_clk.c, 0x01e3 },

		{ &gcc_mdss_pclk1_clk.c, 0x01f8 },

		{ &gcc_mdss_pclk0_clk.c, 0x01f8 },

		{ &gcc_mdss_pclk1_clk.c, 0x01e3 },

		{ &gcc_mdss_mdp_clk.c, 0x01f9 },

		{ &gcc_mdss_vsync_clk.c, 0x01fb },

		{ &gcc_mdss_byte0_clk.c, 0x01e4 },

		{ &gcc_mdss_byte1_clk.c, 0x01fc },

		{ &gcc_mdss_esc0_clk.c, 0x01e5 },

		{ &gcc_mdss_esc1_clk.c, 0x01f8 },

		{ &gcc_mdss_byte0_clk.c, 0x01fc },

		{ &gcc_mdss_byte1_clk.c, 0x01e4 },

		{ &gcc_mdss_esc0_clk.c, 0x01fd },

		{ &gcc_mdss_esc1_clk.c, 0x01e5 },

		{ &wcnss_m_clk.c, 0x0ec },

	),

	.c = {
@@ -3660,7 +3661,6 @@ static struct clk_lookup msm_clocks_lookup_common[] = { 
	CLK_LIST(gcc_prng_ahb_clk),

	CLK_LIST(gcc_cpp_tbu_clk),

	CLK_LIST(gcc_apss_tcu_clk),

	CLK_LIST(gcc_ipa_tbu_clk),

	CLK_LIST(gcc_jpeg_tbu_clk),

	CLK_LIST(gcc_mdp_tbu_clk),

	CLK_LIST(gcc_smmu_cfg_clk),
@@ -4099,6 +4099,10 @@ static struct platform_driver msm_clock_gcc_driver = { 
static int msm_gcc_spm_probe(struct platform_device *pdev)

{

	struct resource *res = NULL;

	bool compat_bin = false;



	compat_bin = of_device_is_compatible(pdev->dev.of_node,

					"qcom,spm-8952");



	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "spm_c0_base");

	if (!res) {
@@ -4126,6 +4130,7 @@ static int msm_gcc_spm_probe(struct platform_device *pdev) 
		return -ENOMEM;

	}



	if (compat_bin) {

		res = platform_get_resource_byname(pdev, IORESOURCE_MEM,

						"spm_cci_base");

		if (!res) {
@@ -4133,12 +4138,13 @@ static int msm_gcc_spm_probe(struct platform_device *pdev) 
			return -ENOMEM;

		}



	a53ss_cci_pll.spm_ctrl.spm_base = devm_ioremap(&pdev->dev, res->start,

						resource_size(res));

		a53ss_cci_pll.spm_ctrl.spm_base = devm_ioremap(&pdev->dev,

						res->start, resource_size(res));

		if (!a53ss_cci_pll.spm_ctrl.spm_base) {

			dev_err(&pdev->dev, "Failed to ioremap cci spm registers\n");

			return -ENOMEM;

		}

	}



	dev_info(&pdev->dev, "Registered GCC SPM clocks\n");
@@ -4147,6 +4153,7 @@ static int msm_gcc_spm_probe(struct platform_device *pdev) 


static struct of_device_id msm_clock_spm_match_table[] = {

	{ .compatible = "qcom,gcc-spm-8952" },

	{ .compatible = "qcom,gcc-spm-8937" },

	{}

};