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Commit 6dbf73e8 authored by Sandeep Panda's avatar Sandeep Panda Committed by Gerrit - the friendly Code Review server
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msm: mdss: update DSI 28nm PHY enable sequence 



This change updates the enable sequence for DSI 28nm PHY
as per HW recommendation.

Change-Id: I9d294e807a40110bfd6c48243fc41b402fcc539d
Signed-off-by: default avatarSandeep Panda <spanda@codeaurora.org>
parent 0191ccd5

drivers/video/msm/mdss/mdss_dsi.h

+1 −1
Original line number Diff line number Diff line
@@ -53,7 +53,7 @@ 
#define MDSS_DSI_HW_REV_101_1		0x10010001	/* 8974Pro */

#define MDSS_DSI_HW_REV_102		0x10020000	/* 8084    */

#define MDSS_DSI_HW_REV_103		0x10030000	/* 8994    */

#define MDSS_DSI_HW_REV_103_1		0x10030001	/* 8916/8936 */

#define MDSS_DSI_HW_REV_103_1		0x10030001	/* 8916/8936/8937 */

#define MDSS_DSI_HW_REV_104             0x10040000      /* 8996   */

#define MDSS_DSI_HW_REV_104_1           0x10040001      /* 8996   */

drivers/video/msm/mdss/msm_mdss_io_8974.c

+13 −10
Original line number Diff line number Diff line
@@ -245,9 +245,13 @@ static void mdss_dsi_28nm_phy_config(struct mdss_dsi_ctrl_pdata *ctrl_pdata) 
	pd = &(((ctrl_pdata->panel_data).panel_info.mipi).dsi_phy_db);



	/* Strength ctrl 0 for 28nm PHY*/

	if ((ctrl_pdata->shared_data->hw_rev <= MDSS_DSI_HW_REV_103) &&

		(ctrl_pdata->shared_data->hw_rev != MDSS_DSI_HW_REV_103))

	if ((ctrl_pdata->shared_data->hw_rev <= MDSS_DSI_HW_REV_103_1) &&

		(ctrl_pdata->shared_data->hw_rev != MDSS_DSI_HW_REV_103)) {

		MIPI_OUTP((ctrl_pdata->phy_io.base) + 0x0170, 0x5b);

		MIPI_OUTP((ctrl_pdata->phy_io.base) + 0x0184, pd->strength[0]);

		/* make sure PHY strength ctrl is set */

		wmb();

	}



	off = 0x0140;	/* phy timing ctrl 0 - 11 */

	for (i = 0; i < 12; i++) {
@@ -256,12 +260,6 @@ static void mdss_dsi_28nm_phy_config(struct mdss_dsi_ctrl_pdata *ctrl_pdata) 
		off += 4;

	}



	/* MMSS_DSI_0_PHY_DSIPHY_CTRL_1 */

	MIPI_OUTP((ctrl_pdata->phy_io.base) + 0x0174, 0x00);

	/* MMSS_DSI_0_PHY_DSIPHY_CTRL_0 */

	MIPI_OUTP((ctrl_pdata->phy_io.base) + 0x0170, 0x5f);

	wmb();



	/* 4 lanes + clk lane configuration */

	/* lane config n * (0 - 4) & DataPath setup */

	for (ln = 0; ln < 5; ln++) {
@@ -275,8 +273,8 @@ static void mdss_dsi_28nm_phy_config(struct mdss_dsi_ctrl_pdata *ctrl_pdata) 
		}

	}



	/* MMSS_DSI_0_PHY_DSIPHY_CTRL_0 */

	MIPI_OUTP((ctrl_pdata->phy_io.base) + 0x0170, 0x5f);

	/* MMSS_DSI_0_PHY_DSIPHY_CTRL_4 */

	MIPI_OUTP((ctrl_pdata->phy_io.base) + 0x0180, 0x0a);

	wmb();



	/* DSI_0_PHY_DSIPHY_GLBL_TEST_CTRL */
@@ -287,6 +285,11 @@ static void mdss_dsi_28nm_phy_config(struct mdss_dsi_ctrl_pdata *ctrl_pdata) 
		MIPI_OUTP((ctrl_pdata->phy_io.base) + 0x01d4, 0x00);

	wmb();



	/* MMSS_DSI_0_PHY_DSIPHY_CTRL_0 */

	MIPI_OUTP((ctrl_pdata->phy_io.base) + 0x0170, 0x5f);

	/* make sure PHY lanes are powered on */

	wmb();



	off = 0x01b4;	/* phy BIST ctrl 0 - 5 */

	for (i = 0; i < 6; i++) {

		MIPI_OUTP((ctrl_pdata->phy_io.base) + off, pd->bistctrl[i]);