msm: mdss: fix the logic for configuration of DSI clock source

The DSI clocks need to sourced out of the correct DSI PLL depending
on the h/w configuration. The current assumption is that the
clk_set_parent operation on DSI branch clocks is necessary for
targets which support 2 DSI PLLs. However, there is a possibility
that the DSI clock source needs to be set even for single DSI
targets if the clock driver implements multi-parent based
approach for DSI RCG clock structures. Add change to take care
of this.

Change-Id: Ib399a8264d0d9919701c70ed6a77d50a69ec386c
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>