Loading drivers/video/msm/mdss/mdss_dsi_host.c +19 −0 Original line number Diff line number Diff line Loading @@ -1714,6 +1714,25 @@ static int mdss_dsi_cmd_dma_tx(struct mdss_dsi_ctrl_pdata *ctrl, ret = wait_for_completion_timeout(&ctrl->dma_comp, msecs_to_jiffies(DMA_TX_TIMEOUT)); if (ret <= 0) { u32 reg_val, status, mask; reg_val = MIPI_INP(ctrl->ctrl_base + 0x0110);/* DSI_INTR_CTRL */ mask = reg_val & DSI_INTR_CMD_DMA_DONE_MASK; status = mask & reg_val; if (status) { pr_warn("dma tx done but irq not triggered\n"); reg_val &= DSI_INTR_MASK_ALL; /* clear CMD DMA isr only */ reg_val |= DSI_INTR_CMD_DMA_DONE; MIPI_OUTP(ctrl->ctrl_base + 0x0110, reg_val); mdss_dsi_disable_irq_nosync(ctrl, DSI_MDP_TERM); complete(&ctrl->dma_comp); ret = 1; } } if (ret == 0) ret = -ETIMEDOUT; else Loading Loading
drivers/video/msm/mdss/mdss_dsi_host.c +19 −0 Original line number Diff line number Diff line Loading @@ -1714,6 +1714,25 @@ static int mdss_dsi_cmd_dma_tx(struct mdss_dsi_ctrl_pdata *ctrl, ret = wait_for_completion_timeout(&ctrl->dma_comp, msecs_to_jiffies(DMA_TX_TIMEOUT)); if (ret <= 0) { u32 reg_val, status, mask; reg_val = MIPI_INP(ctrl->ctrl_base + 0x0110);/* DSI_INTR_CTRL */ mask = reg_val & DSI_INTR_CMD_DMA_DONE_MASK; status = mask & reg_val; if (status) { pr_warn("dma tx done but irq not triggered\n"); reg_val &= DSI_INTR_MASK_ALL; /* clear CMD DMA isr only */ reg_val |= DSI_INTR_CMD_DMA_DONE; MIPI_OUTP(ctrl->ctrl_base + 0x0110, reg_val); mdss_dsi_disable_irq_nosync(ctrl, DSI_MDP_TERM); complete(&ctrl->dma_comp); ret = 1; } } if (ret == 0) ret = -ETIMEDOUT; else Loading