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Commit 6d3a1741 authored by Bjorn Helgaas's avatar Bjorn Helgaas
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PCI: Support PCIe Capability Slot registers only for ports with slots 



Previously we allowed callers to access Slot Capabilities, Status, and
Control for Root Ports even if the Root Port did not implement a slot.
This seems dubious because the spec only requires these registers if a
slot is implemented.

It's true that even Root Ports without slots must have *space* for these
slot registers, because the Root Capabilities, Status, and Control
registers are after the slot registers in the capability.  However,
for a v1 PCIe Capability, the *semantics* of the slot registers are
undefined unless a slot is implemented.

Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
Reviewed-By: default avatarJiang Liu <jiang.liu@huawei.com>
parent c8b303d0

drivers/pci/access.c

+3 −3
Original line number Diff line number Diff line
@@ -497,9 +497,9 @@ static inline bool pcie_cap_has_sltctl(const struct pci_dev *dev) 
{

	int type = pci_pcie_type(dev);



	return type == PCI_EXP_TYPE_ROOT_PORT ||

	       (type == PCI_EXP_TYPE_DOWNSTREAM &&

		pcie_caps_reg(dev) & PCI_EXP_FLAGS_SLOT);

	return (type == PCI_EXP_TYPE_ROOT_PORT ||

		type == PCI_EXP_TYPE_DOWNSTREAM) &&

	       pcie_caps_reg(dev) & PCI_EXP_FLAGS_SLOT;

}



static inline bool pcie_cap_has_rtctl(const struct pci_dev *dev)