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Commit 6c725002 authored by Mallikarjuna Reddy Amireddy's avatar Mallikarjuna Reddy Amireddy
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ARM: dts: msm: Add crypto device tree nodes for MDM9X07 



Add qcedev and qcrypto device tree nodes to support HW crypto
functionality on mdm9x07.

Change-Id: I2c11c9511d8b10b0a25e408249c18a18db8e7435
Signed-off-by: default avatarMallikarjuna Reddy Amireddy <mamire@codeaurora.org>
parent fcbbe260

arch/arm/boot/dts/qcom/mdm9607.dtsi

+56 −0
Original line number Diff line number Diff line
@@ -1501,6 +1501,62 @@ 
		status = "disabled";

	};



	qcom_crypto: qcrypto@720000 {

		compatible = "qcom,qcrypto";

		reg = <0x720000 0x20000>,

			<0x704000 0x20000>;

		reg-names = "crypto-base","crypto-bam-base";

		interrupts = <0 207 0>;

		qcom,bam-pipe-pair = <2>;

		qcom,ce-hw-instance = <0>;

		qcom,ce-device = <0>;

		qcom,clk-mgmt-sus-res;

		qcom,msm-bus,name = "qcrypto-noc";

		qcom,msm-bus,num-cases = <2>;

		qcom,msm-bus,num-paths = <1>;

		qcom,msm-bus,vectors-KBps =

				<47 512 0 0>,

				<47 512 393600 800000>;

		clocks = <&clock_gcc clk_crypto_clk_src>,

			 <&clock_gcc clk_gcc_crypto_clk>,

			 <&clock_gcc clk_gcc_crypto_ahb_clk>,

			 <&clock_gcc clk_gcc_crypto_axi_clk>;

		clock-names = "core_clk_src", "core_clk",

				"iface_clk", "bus_clk";

		qcom,use-sw-aes-cbc-ecb-ctr-algo;

		qcom,use-sw-aes-xts-algo;

		qcom,use-sw-aes-ccm-algo;

		qcom,use-sw-ahash-algo;

		qcom,use-sw-hmac-algo;

		qcom,use-sw-aead-algo;

		qcom,ce-opp-freq = <100000000>;

	};



	qcom_qcedev: qcedev@720000 {

		compatible = "qcom,qcedev";

		reg = <0x720000 0x20000>,

			<0x704000 0x20000>;

		reg-names = "crypto-base","crypto-bam-base";

		interrupts = <0 207 0>;

		qcom,bam-pipe-pair = <1>;

		qcom,ce-hw-instance = <0>;

		qcom,ce-device = <0>;

		qcom,ce-hw-shared;

		qcom,msm-bus,name = "qcedev-noc";

		qcom,msm-bus,num-cases = <2>;

		qcom,msm-bus,num-paths = <1>;

		qcom,msm-bus,vectors-KBps =

				<47 512 0 0>,

				<47 512 3936000 393600>;

		clocks = <&clock_gcc clk_crypto_clk_src>,

			 <&clock_gcc clk_gcc_crypto_clk>,

			 <&clock_gcc clk_gcc_crypto_ahb_clk>,

			 <&clock_gcc clk_gcc_crypto_axi_clk>;

		clock-names = "core_clk_src", "core_clk",

				"iface_clk", "bus_clk";

		qcom,ce-opp-freq = <100000000>;

	};



	emac0: qcom,emac@7c40000 {

		cell-index = <0>;

		compatible = "qcom,mdm9607-emac";