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Commit 6c4ba025 authored by Sahitya Tummala's avatar Sahitya Tummala
Browse files

mtd: msm_qpic_nand: Fix the opcode used in raw write mode 



MTD_OPS_RAW mode should allow the ECC and Spare bytes to be
written from the buffer that user provides. For this, the
opcode[3:0] 0x9 must be programmed into QPIC_NAND_FLASH_CMD
register. But the current code incorrectly uses opcode[3:0]
0x6 which doesn't allow ECC/spare bytes to be written when
ECC is disabled.

Change-Id: I1ae8a8a59e691f275c369a64b93e190fa27a0655
Signed-off-by: default avatarSahitya Tummala <stummala@codeaurora.org>
parent be05b187

drivers/mtd/devices/msm_qpic_nand.c

+2 −1
Original line number Diff line number Diff line
@@ -1063,15 +1063,16 @@ static void msm_nand_update_rw_reg_data(struct msm_nand_chip *chip, 


	} else {

		if (ops->mode != MTD_OPS_RAW) {

			data->cmd = MSM_NAND_CMD_PRG_PAGE;

			data->cfg0 = chip->cfg0;

			data->cfg1 = chip->cfg1;

			data->ecc_bch_cfg = chip->ecc_bch_cfg;

		} else {

			data->cmd = MSM_NAND_CMD_PRG_PAGE_ALL;

			data->cfg0 = chip->cfg0_raw;

			data->cfg1 = chip->cfg1_raw;

			data->ecc_bch_cfg = chip->ecc_cfg_raw;

		}

		data->cmd = MSM_NAND_CMD_PRG_PAGE;

		data->clrfstatus = MSM_NAND_RESET_FLASH_STS;

		data->clrrstatus = MSM_NAND_RESET_READ_STS;

	}