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Commit 6c4443d7 authored by Mallikarjuna Reddy Amireddy's avatar Mallikarjuna Reddy Amireddy Committed by Gerrit - the friendly Code Review server
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ARM: dts: msm: Add qseecom device tree data for msmgold 



Add QSEECOM device node with required parameters to enable qseecom
driver which is a interface between non-secure applications that
exist on the HLOS and the secure applications that reside on QSEE.

Change-Id: I0a19faa18bf8cbcd016e8502c5040d59da136e72
Signed-off-by: default avatarMallikarjuna Reddy Amireddy <mamire@codeaurora.org>
parent a34de1ec

arch/arm/boot/dts/qcom/msmgold.dtsi

+27 −0
Original line number Diff line number Diff line
@@ -1233,6 +1233,33 @@ 
		qcom,ce-opp-freq = <100000000>;

	};



	qcom_seecom: qseecom@85e00000 {

		compatible = "qcom,qseecom";

		reg = <0x85e00000 0x500000>;

		reg-names = "secapp-region";

		qcom,hlos-num-ce-hw-instances = <1>;

		qcom,hlos-ce-hw-instance = <0>;

		qcom,qsee-ce-hw-instance = <0>;

		qcom,disk-encrypt-pipe-pair = <2>;

		qcom,support-fde;

		qcom,msm-bus,name = "qseecom-noc";

		qcom,msm-bus,num-cases = <4>;

		qcom,msm-bus,num-paths = <1>;

		qcom,support-bus-scaling;

		qcom,msm-bus,vectors-KBps =

			<55 512 0 0>,

			<55 512 0 0>,

			<55 512 120000 1200000>,

			<55 512 393600 3936000>;

		clocks = <&clock_gcc clk_crypto_clk_src>,

			 <&clock_gcc clk_gcc_crypto_clk>,

			 <&clock_gcc clk_gcc_crypto_ahb_clk>,

			 <&clock_gcc clk_gcc_crypto_axi_clk>;

		clock-names = "core_clk_src", "core_clk",

				"iface_clk", "bus_clk";

		qcom,ce-opp-freq = <100000000>;

	};



	qcom,iris-fm {

		compatible = "qcom,iris_fm";

	};