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Commit 6b3da11b authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'for-3.3' of git://git.kernel.org/pub/scm/linux/kernel/git/tj/percpu 

* 'for-3.3' of git://git.kernel.org/pub/scm/linux/kernel/git/tj/percpu:
  percpu: Remove irqsafe_cpu_xxx variants

Fix up conflict in arch/x86/include/asm/percpu.h due to clash with
cebef5be ("x86: Fix and improve percpu_cmpxchg{8,16}b_double()")
which edited the (now removed) irqsafe_cpu_cmpxchg*_double code.
parents db0c2bf6 933393f5

arch/s390/include/asm/percpu.h

+22 −22
Original line number Diff line number Diff line
@@ -19,7 +19,7 @@ 
#define ARCH_NEEDS_WEAK_PER_CPU

#endif



#define arch_irqsafe_cpu_to_op(pcp, val, op)				\

#define arch_this_cpu_to_op(pcp, val, op)				\

do {									\

	typedef typeof(pcp) pcp_op_T__;					\

	pcp_op_T__ old__, new__, prev__;				\
@@ -41,27 +41,27 @@ do { \ 
	preempt_enable();						\

} while (0)



#define irqsafe_cpu_add_1(pcp, val) arch_irqsafe_cpu_to_op(pcp, val, +)

#define irqsafe_cpu_add_2(pcp, val) arch_irqsafe_cpu_to_op(pcp, val, +)

#define irqsafe_cpu_add_4(pcp, val) arch_irqsafe_cpu_to_op(pcp, val, +)

#define irqsafe_cpu_add_8(pcp, val) arch_irqsafe_cpu_to_op(pcp, val, +)

#define this_cpu_add_1(pcp, val) arch_this_cpu_to_op(pcp, val, +)

#define this_cpu_add_2(pcp, val) arch_this_cpu_to_op(pcp, val, +)

#define this_cpu_add_4(pcp, val) arch_this_cpu_to_op(pcp, val, +)

#define this_cpu_add_8(pcp, val) arch_this_cpu_to_op(pcp, val, +)



#define irqsafe_cpu_and_1(pcp, val) arch_irqsafe_cpu_to_op(pcp, val, &)

#define irqsafe_cpu_and_2(pcp, val) arch_irqsafe_cpu_to_op(pcp, val, &)

#define irqsafe_cpu_and_4(pcp, val) arch_irqsafe_cpu_to_op(pcp, val, &)

#define irqsafe_cpu_and_8(pcp, val) arch_irqsafe_cpu_to_op(pcp, val, &)

#define this_cpu_and_1(pcp, val) arch_this_cpu_to_op(pcp, val, &)

#define this_cpu_and_2(pcp, val) arch_this_cpu_to_op(pcp, val, &)

#define this_cpu_and_4(pcp, val) arch_this_cpu_to_op(pcp, val, &)

#define this_cpu_and_8(pcp, val) arch_this_cpu_to_op(pcp, val, &)



#define irqsafe_cpu_or_1(pcp, val) arch_irqsafe_cpu_to_op(pcp, val, |)

#define irqsafe_cpu_or_2(pcp, val) arch_irqsafe_cpu_to_op(pcp, val, |)

#define irqsafe_cpu_or_4(pcp, val) arch_irqsafe_cpu_to_op(pcp, val, |)

#define irqsafe_cpu_or_8(pcp, val) arch_irqsafe_cpu_to_op(pcp, val, |)

#define this_cpu_or_1(pcp, val) arch_this_cpu_to_op(pcp, val, |)

#define this_cpu_or_2(pcp, val) arch_this_cpu_to_op(pcp, val, |)

#define this_cpu_or_4(pcp, val) arch_this_cpu_to_op(pcp, val, |)

#define this_cpu_or_8(pcp, val) arch_this_cpu_to_op(pcp, val, |)



#define irqsafe_cpu_xor_1(pcp, val) arch_irqsafe_cpu_to_op(pcp, val, ^)

#define irqsafe_cpu_xor_2(pcp, val) arch_irqsafe_cpu_to_op(pcp, val, ^)

#define irqsafe_cpu_xor_4(pcp, val) arch_irqsafe_cpu_to_op(pcp, val, ^)

#define irqsafe_cpu_xor_8(pcp, val) arch_irqsafe_cpu_to_op(pcp, val, ^)

#define this_cpu_xor_1(pcp, val) arch_this_cpu_to_op(pcp, val, ^)

#define this_cpu_xor_2(pcp, val) arch_this_cpu_to_op(pcp, val, ^)

#define this_cpu_xor_4(pcp, val) arch_this_cpu_to_op(pcp, val, ^)

#define this_cpu_xor_8(pcp, val) arch_this_cpu_to_op(pcp, val, ^)



#define arch_irqsafe_cpu_cmpxchg(pcp, oval, nval)			\

#define arch_this_cpu_cmpxchg(pcp, oval, nval)			\

({									\

	typedef typeof(pcp) pcp_op_T__;					\

	pcp_op_T__ ret__;						\
@@ -79,10 +79,10 @@ do { \ 
	ret__;								\

})



#define irqsafe_cpu_cmpxchg_1(pcp, oval, nval) arch_irqsafe_cpu_cmpxchg(pcp, oval, nval)

#define irqsafe_cpu_cmpxchg_2(pcp, oval, nval) arch_irqsafe_cpu_cmpxchg(pcp, oval, nval)

#define irqsafe_cpu_cmpxchg_4(pcp, oval, nval) arch_irqsafe_cpu_cmpxchg(pcp, oval, nval)

#define irqsafe_cpu_cmpxchg_8(pcp, oval, nval) arch_irqsafe_cpu_cmpxchg(pcp, oval, nval)

#define this_cpu_cmpxchg_1(pcp, oval, nval) arch_this_cpu_cmpxchg(pcp, oval, nval)

#define this_cpu_cmpxchg_2(pcp, oval, nval) arch_this_cpu_cmpxchg(pcp, oval, nval)

#define this_cpu_cmpxchg_4(pcp, oval, nval) arch_this_cpu_cmpxchg(pcp, oval, nval)

#define this_cpu_cmpxchg_8(pcp, oval, nval) arch_this_cpu_cmpxchg(pcp, oval, nval)



#include <asm-generic/percpu.h>

arch/x86/include/asm/percpu.h

+0 −28
Original line number Diff line number Diff line
@@ -414,22 +414,6 @@ do { \ 
#define this_cpu_xchg_2(pcp, nval)	percpu_xchg_op(pcp, nval)

#define this_cpu_xchg_4(pcp, nval)	percpu_xchg_op(pcp, nval)



#define irqsafe_cpu_add_1(pcp, val)	percpu_add_op((pcp), val)

#define irqsafe_cpu_add_2(pcp, val)	percpu_add_op((pcp), val)

#define irqsafe_cpu_add_4(pcp, val)	percpu_add_op((pcp), val)

#define irqsafe_cpu_and_1(pcp, val)	percpu_to_op("and", (pcp), val)

#define irqsafe_cpu_and_2(pcp, val)	percpu_to_op("and", (pcp), val)

#define irqsafe_cpu_and_4(pcp, val)	percpu_to_op("and", (pcp), val)

#define irqsafe_cpu_or_1(pcp, val)	percpu_to_op("or", (pcp), val)

#define irqsafe_cpu_or_2(pcp, val)	percpu_to_op("or", (pcp), val)

#define irqsafe_cpu_or_4(pcp, val)	percpu_to_op("or", (pcp), val)

#define irqsafe_cpu_xor_1(pcp, val)	percpu_to_op("xor", (pcp), val)

#define irqsafe_cpu_xor_2(pcp, val)	percpu_to_op("xor", (pcp), val)

#define irqsafe_cpu_xor_4(pcp, val)	percpu_to_op("xor", (pcp), val)

#define irqsafe_cpu_xchg_1(pcp, nval)	percpu_xchg_op(pcp, nval)

#define irqsafe_cpu_xchg_2(pcp, nval)	percpu_xchg_op(pcp, nval)

#define irqsafe_cpu_xchg_4(pcp, nval)	percpu_xchg_op(pcp, nval)



#ifndef CONFIG_M386

#define __this_cpu_add_return_1(pcp, val) percpu_add_return_op(pcp, val)

#define __this_cpu_add_return_2(pcp, val) percpu_add_return_op(pcp, val)
@@ -445,9 +429,6 @@ do { \ 
#define this_cpu_cmpxchg_2(pcp, oval, nval)	percpu_cmpxchg_op(pcp, oval, nval)

#define this_cpu_cmpxchg_4(pcp, oval, nval)	percpu_cmpxchg_op(pcp, oval, nval)



#define irqsafe_cpu_cmpxchg_1(pcp, oval, nval)	percpu_cmpxchg_op(pcp, oval, nval)

#define irqsafe_cpu_cmpxchg_2(pcp, oval, nval)	percpu_cmpxchg_op(pcp, oval, nval)

#define irqsafe_cpu_cmpxchg_4(pcp, oval, nval)	percpu_cmpxchg_op(pcp, oval, nval)

#endif /* !CONFIG_M386 */



#ifdef CONFIG_X86_CMPXCHG64
@@ -464,7 +445,6 @@ do { \ 


#define __this_cpu_cmpxchg_double_4	percpu_cmpxchg8b_double

#define this_cpu_cmpxchg_double_4	percpu_cmpxchg8b_double

#define irqsafe_cpu_cmpxchg_double_4	percpu_cmpxchg8b_double

#endif /* CONFIG_X86_CMPXCHG64 */



/*
@@ -492,13 +472,6 @@ do { \ 
#define this_cpu_xchg_8(pcp, nval)	percpu_xchg_op(pcp, nval)

#define this_cpu_cmpxchg_8(pcp, oval, nval)	percpu_cmpxchg_op(pcp, oval, nval)



#define irqsafe_cpu_add_8(pcp, val)	percpu_add_op((pcp), val)

#define irqsafe_cpu_and_8(pcp, val)	percpu_to_op("and", (pcp), val)

#define irqsafe_cpu_or_8(pcp, val)	percpu_to_op("or", (pcp), val)

#define irqsafe_cpu_xor_8(pcp, val)	percpu_to_op("xor", (pcp), val)

#define irqsafe_cpu_xchg_8(pcp, nval)	percpu_xchg_op(pcp, nval)

#define irqsafe_cpu_cmpxchg_8(pcp, oval, nval)	percpu_cmpxchg_op(pcp, oval, nval)



/*

 * Pretty complex macro to generate cmpxchg16 instruction.  The instruction

 * is not supported on early AMD64 processors so we must be able to emulate
@@ -521,7 +494,6 @@ do { \ 


#define __this_cpu_cmpxchg_double_8	percpu_cmpxchg16b_double

#define this_cpu_cmpxchg_double_8	percpu_cmpxchg16b_double

#define irqsafe_cpu_cmpxchg_double_8	percpu_cmpxchg16b_double



#endif

include/linux/netdevice.h

+2 −2
Original line number Diff line number Diff line
@@ -2155,7 +2155,7 @@ extern void netdev_run_todo(void); 
 */

static inline void dev_put(struct net_device *dev)

{

	irqsafe_cpu_dec(*dev->pcpu_refcnt);

	this_cpu_dec(*dev->pcpu_refcnt);

}



/**
@@ -2166,7 +2166,7 @@ static inline void dev_put(struct net_device *dev) 
 */

static inline void dev_hold(struct net_device *dev)

{

	irqsafe_cpu_inc(*dev->pcpu_refcnt);

	this_cpu_inc(*dev->pcpu_refcnt);

}



/* Carrier loss detection, dial on demand. The functions netif_carrier_on

include/linux/netfilter/x_tables.h

+2 −2
Original line number Diff line number Diff line
@@ -471,7 +471,7 @@ DECLARE_PER_CPU(seqcount_t, xt_recseq); 
 *

 * Begin packet processing : all readers must wait the end

 * 1) Must be called with preemption disabled

 * 2) softirqs must be disabled too (or we should use irqsafe_cpu_add())

 * 2) softirqs must be disabled too (or we should use this_cpu_add())

 * Returns :

 *  1 if no recursion on this cpu

 *  0 if recursion detected
@@ -503,7 +503,7 @@ static inline unsigned int xt_write_recseq_begin(void) 
 *

 * End packet processing : all readers can proceed

 * 1) Must be called with preemption disabled

 * 2) softirqs must be disabled too (or we should use irqsafe_cpu_add())

 * 2) softirqs must be disabled too (or we should use this_cpu_add())

 */

static inline void xt_write_recseq_end(unsigned int addend)

{

include/linux/percpu.h

+22 −168
Original line number Diff line number Diff line
@@ -172,10 +172,10 @@ extern phys_addr_t per_cpu_ptr_to_phys(void *addr); 
 * equal char, int or long.  percpu_read() evaluates to a lvalue and

 * all others to void.

 *

 * These operations are guaranteed to be atomic w.r.t. preemption.

 * The generic versions use plain get/put_cpu_var().  Archs are

 * These operations are guaranteed to be atomic.

 * The generic versions disable interrupts.  Archs are

 * encouraged to implement single-instruction alternatives which don't

 * require preemption protection.

 * require protection.

 */

#ifndef percpu_read

# define percpu_read(var)						\
@@ -347,9 +347,10 @@ do { \ 


#define _this_cpu_generic_to_op(pcp, val, op)				\

do {									\

	preempt_disable();						\

	unsigned long flags;						\

	local_irq_save(flags);						\

	*__this_cpu_ptr(&(pcp)) op val;					\

	preempt_enable();						\

	local_irq_restore(flags);					\

} while (0)



#ifndef this_cpu_write
@@ -447,10 +448,11 @@ do { \ 
#define _this_cpu_generic_add_return(pcp, val)				\

({									\

	typeof(pcp) ret__;						\

	preempt_disable();						\

	unsigned long flags;						\

	local_irq_save(flags);						\

	__this_cpu_add(pcp, val);					\

	ret__ = __this_cpu_read(pcp);					\

	preempt_enable();						\

	local_irq_restore(flags);					\

	ret__;								\

})
@@ -476,10 +478,11 @@ do { \ 


#define _this_cpu_generic_xchg(pcp, nval)				\

({	typeof(pcp) ret__;						\

	preempt_disable();						\

	unsigned long flags;						\

	local_irq_save(flags);						\

	ret__ = __this_cpu_read(pcp);					\

	__this_cpu_write(pcp, nval);					\

	preempt_enable();						\

	local_irq_restore(flags);					\

	ret__;								\

})
@@ -501,12 +504,14 @@ do { \ 
#endif



#define _this_cpu_generic_cmpxchg(pcp, oval, nval)			\

({	typeof(pcp) ret__;						\

	preempt_disable();						\

({									\

	typeof(pcp) ret__;						\

	unsigned long flags;						\

	local_irq_save(flags);						\

	ret__ = __this_cpu_read(pcp);					\

	if (ret__ == (oval))						\

		__this_cpu_write(pcp, nval);				\

	preempt_enable();						\

	local_irq_restore(flags);					\

	ret__;								\

})
@@ -538,10 +543,11 @@ do { \ 
#define _this_cpu_generic_cmpxchg_double(pcp1, pcp2, oval1, oval2, nval1, nval2)	\

({									\

	int ret__;							\

	preempt_disable();						\

	unsigned long flags;						\

	local_irq_save(flags);						\

	ret__ = __this_cpu_generic_cmpxchg_double(pcp1, pcp2,		\

			oval1, oval2, nval1, nval2);			\

	preempt_enable();						\

	local_irq_restore(flags);					\

	ret__;								\

})
@@ -567,9 +573,9 @@ do { \ 
#endif



/*

 * Generic percpu operations that do not require preemption handling.

 * Generic percpu operations for context that are safe from preemption/interrupts.

 * Either we do not care about races or the caller has the

 * responsibility of handling preemptions issues. Arch code can still

 * responsibility of handling preemption/interrupt issues. Arch code can still

 * override these instructions since the arch per cpu code may be more

 * efficient and may actually get race freeness for free (that is the

 * case for x86 for example).
@@ -802,156 +808,4 @@ do { \ 
	__pcpu_double_call_return_bool(__this_cpu_cmpxchg_double_, (pcp1), (pcp2), (oval1), (oval2), (nval1), (nval2))

#endif



/*

 * IRQ safe versions of the per cpu RMW operations. Note that these operations

 * are *not* safe against modification of the same variable from another

 * processors (which one gets when using regular atomic operations)

 * They are guaranteed to be atomic vs. local interrupts and

 * preemption only.

 */

#define irqsafe_cpu_generic_to_op(pcp, val, op)				\

do {									\

	unsigned long flags;						\

	local_irq_save(flags);						\

	*__this_cpu_ptr(&(pcp)) op val;					\

	local_irq_restore(flags);					\

} while (0)



#ifndef irqsafe_cpu_add

# ifndef irqsafe_cpu_add_1

#  define irqsafe_cpu_add_1(pcp, val) irqsafe_cpu_generic_to_op((pcp), (val), +=)

# endif

# ifndef irqsafe_cpu_add_2

#  define irqsafe_cpu_add_2(pcp, val) irqsafe_cpu_generic_to_op((pcp), (val), +=)

# endif

# ifndef irqsafe_cpu_add_4

#  define irqsafe_cpu_add_4(pcp, val) irqsafe_cpu_generic_to_op((pcp), (val), +=)

# endif

# ifndef irqsafe_cpu_add_8

#  define irqsafe_cpu_add_8(pcp, val) irqsafe_cpu_generic_to_op((pcp), (val), +=)

# endif

# define irqsafe_cpu_add(pcp, val) __pcpu_size_call(irqsafe_cpu_add_, (pcp), (val))

#endif



#ifndef irqsafe_cpu_sub

# define irqsafe_cpu_sub(pcp, val)	irqsafe_cpu_add((pcp), -(val))

#endif



#ifndef irqsafe_cpu_inc

# define irqsafe_cpu_inc(pcp)	irqsafe_cpu_add((pcp), 1)

#endif



#ifndef irqsafe_cpu_dec

# define irqsafe_cpu_dec(pcp)	irqsafe_cpu_sub((pcp), 1)

#endif



#ifndef irqsafe_cpu_and

# ifndef irqsafe_cpu_and_1

#  define irqsafe_cpu_and_1(pcp, val) irqsafe_cpu_generic_to_op((pcp), (val), &=)

# endif

# ifndef irqsafe_cpu_and_2

#  define irqsafe_cpu_and_2(pcp, val) irqsafe_cpu_generic_to_op((pcp), (val), &=)

# endif

# ifndef irqsafe_cpu_and_4

#  define irqsafe_cpu_and_4(pcp, val) irqsafe_cpu_generic_to_op((pcp), (val), &=)

# endif

# ifndef irqsafe_cpu_and_8

#  define irqsafe_cpu_and_8(pcp, val) irqsafe_cpu_generic_to_op((pcp), (val), &=)

# endif

# define irqsafe_cpu_and(pcp, val) __pcpu_size_call(irqsafe_cpu_and_, (val))

#endif



#ifndef irqsafe_cpu_or

# ifndef irqsafe_cpu_or_1

#  define irqsafe_cpu_or_1(pcp, val) irqsafe_cpu_generic_to_op((pcp), (val), |=)

# endif

# ifndef irqsafe_cpu_or_2

#  define irqsafe_cpu_or_2(pcp, val) irqsafe_cpu_generic_to_op((pcp), (val), |=)

# endif

# ifndef irqsafe_cpu_or_4

#  define irqsafe_cpu_or_4(pcp, val) irqsafe_cpu_generic_to_op((pcp), (val), |=)

# endif

# ifndef irqsafe_cpu_or_8

#  define irqsafe_cpu_or_8(pcp, val) irqsafe_cpu_generic_to_op((pcp), (val), |=)

# endif

# define irqsafe_cpu_or(pcp, val) __pcpu_size_call(irqsafe_cpu_or_, (val))

#endif



#ifndef irqsafe_cpu_xor

# ifndef irqsafe_cpu_xor_1

#  define irqsafe_cpu_xor_1(pcp, val) irqsafe_cpu_generic_to_op((pcp), (val), ^=)

# endif

# ifndef irqsafe_cpu_xor_2

#  define irqsafe_cpu_xor_2(pcp, val) irqsafe_cpu_generic_to_op((pcp), (val), ^=)

# endif

# ifndef irqsafe_cpu_xor_4

#  define irqsafe_cpu_xor_4(pcp, val) irqsafe_cpu_generic_to_op((pcp), (val), ^=)

# endif

# ifndef irqsafe_cpu_xor_8

#  define irqsafe_cpu_xor_8(pcp, val) irqsafe_cpu_generic_to_op((pcp), (val), ^=)

# endif

# define irqsafe_cpu_xor(pcp, val) __pcpu_size_call(irqsafe_cpu_xor_, (val))

#endif



#define irqsafe_cpu_generic_cmpxchg(pcp, oval, nval)			\

({									\

	typeof(pcp) ret__;						\

	unsigned long flags;						\

	local_irq_save(flags);						\

	ret__ = __this_cpu_read(pcp);					\

	if (ret__ == (oval))						\

		__this_cpu_write(pcp, nval);				\

	local_irq_restore(flags);					\

	ret__;								\

})



#ifndef irqsafe_cpu_cmpxchg

# ifndef irqsafe_cpu_cmpxchg_1

#  define irqsafe_cpu_cmpxchg_1(pcp, oval, nval)	irqsafe_cpu_generic_cmpxchg(pcp, oval, nval)

# endif

# ifndef irqsafe_cpu_cmpxchg_2

#  define irqsafe_cpu_cmpxchg_2(pcp, oval, nval)	irqsafe_cpu_generic_cmpxchg(pcp, oval, nval)

# endif

# ifndef irqsafe_cpu_cmpxchg_4

#  define irqsafe_cpu_cmpxchg_4(pcp, oval, nval)	irqsafe_cpu_generic_cmpxchg(pcp, oval, nval)

# endif

# ifndef irqsafe_cpu_cmpxchg_8

#  define irqsafe_cpu_cmpxchg_8(pcp, oval, nval)	irqsafe_cpu_generic_cmpxchg(pcp, oval, nval)

# endif

# define irqsafe_cpu_cmpxchg(pcp, oval, nval)		\

	__pcpu_size_call_return2(irqsafe_cpu_cmpxchg_, (pcp), oval, nval)

#endif



#define irqsafe_generic_cpu_cmpxchg_double(pcp1, pcp2, oval1, oval2, nval1, nval2)	\

({									\

	int ret__;							\

	unsigned long flags;						\

	local_irq_save(flags);						\

	ret__ = __this_cpu_generic_cmpxchg_double(pcp1, pcp2,		\

			oval1, oval2, nval1, nval2);			\

	local_irq_restore(flags);					\

	ret__;								\

})



#ifndef irqsafe_cpu_cmpxchg_double

# ifndef irqsafe_cpu_cmpxchg_double_1

#  define irqsafe_cpu_cmpxchg_double_1(pcp1, pcp2, oval1, oval2, nval1, nval2)	\

	irqsafe_generic_cpu_cmpxchg_double(pcp1, pcp2, oval1, oval2, nval1, nval2)

# endif

# ifndef irqsafe_cpu_cmpxchg_double_2

#  define irqsafe_cpu_cmpxchg_double_2(pcp1, pcp2, oval1, oval2, nval1, nval2)	\

	irqsafe_generic_cpu_cmpxchg_double(pcp1, pcp2, oval1, oval2, nval1, nval2)

# endif

# ifndef irqsafe_cpu_cmpxchg_double_4

#  define irqsafe_cpu_cmpxchg_double_4(pcp1, pcp2, oval1, oval2, nval1, nval2)	\

	irqsafe_generic_cpu_cmpxchg_double(pcp1, pcp2, oval1, oval2, nval1, nval2)

# endif

# ifndef irqsafe_cpu_cmpxchg_double_8

#  define irqsafe_cpu_cmpxchg_double_8(pcp1, pcp2, oval1, oval2, nval1, nval2)	\

	irqsafe_generic_cpu_cmpxchg_double(pcp1, pcp2, oval1, oval2, nval1, nval2)

# endif

# define irqsafe_cpu_cmpxchg_double(pcp1, pcp2, oval1, oval2, nval1, nval2)	\

	__pcpu_double_call_return_bool(irqsafe_cpu_cmpxchg_double_, (pcp1), (pcp2), (oval1), (oval2), (nval1), (nval2))

#endif



#endif /* __LINUX_PERCPU_H */