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Commit 6b07d7fe authored by Catalin Marinas's avatar Catalin Marinas
Browse files

ARMv7: Do not set TTBR0 in __v7_setup 



This register is set in __enable_mmu in the head.S file.

Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent 376e1421

arch/arm/mm/proc-v7.S

+0 −1
Original line number Diff line number Diff line
@@ -175,7 +175,6 @@ __v7_setup: 
	mcr	p15, 0, r10, c8, c7, 0		@ invalidate I + D TLBs

	mcr	p15, 0, r10, c2, c0, 2		@ TTB control register

	orr	r4, r4, #TTB_RGN_OC_WB		@ mark PTWs outer cacheable, WB

	mcr	p15, 0, r4, c2, c0, 0		@ load TTB0

	mcr	p15, 0, r4, c2, c0, 1		@ load TTB1

	mov	r10, #0x1f			@ domains 0, 1 = manager

	mcr	p15, 0, r10, c3, c0, 0		@ load domain access register