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Commit 6af9cd14 authored Jan 31, 2011 by Archit Taneja Committed by Tomi Valkeinen Mar 11, 2011

OMAP2PLUS: DSS2: Generalize naming of PRCM related clock enums in DSS driver



enum dss_clock structure is replaced with generic names that
could be used across OMAP2420, 2430, 3xxx, 44xx platforms.

Signed-off-by: Sumit Semwal <sumit.semwal@ti.com>
Signed-off-by: Archit Taneja <archit@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>

parent 872462cd

drivers/video/omap2/dss/core.c

+2 −2

Original line number	Original line	Diff line number	Diff line
	@@ -184,7 +184,7 @@ static int omap_dss_probe(struct platform_device *pdev)
	}		}

	/* keep clocks enabled to prevent context saves/restores during init */		/* keep clocks enabled to prevent context saves/restores during init */
	dss_clk_enable(DSS_CLK_ICK \| DSS_CLK_FCK1);		dss_clk_enable(DSS_CLK_ICK \| DSS_CLK_FCK);

	r = rfbi_init_platform_driver();		r = rfbi_init_platform_driver();
	if (r) {		if (r) {
	@@ -251,7 +251,7 @@ static int omap_dss_probe(struct platform_device *pdev)
	pdata->default_device = dssdev;		pdata->default_device = dssdev;
	}		}

	dss_clk_disable(DSS_CLK_ICK \| DSS_CLK_FCK1);		dss_clk_disable(DSS_CLK_ICK \| DSS_CLK_FCK);

	return 0;		return 0;

drivers/video/omap2/dss/dispc.c

+5 −5

Original line number	Original line	Diff line number	Diff line
	@@ -551,9 +551,9 @@ void dispc_restore_context(void)
	static inline void enable_clocks(bool enable)		static inline void enable_clocks(bool enable)
	{		{
	if (enable)		if (enable)
	dss_clk_enable(DSS_CLK_ICK \| DSS_CLK_FCK1);		dss_clk_enable(DSS_CLK_ICK \| DSS_CLK_FCK);
	else		else
	dss_clk_disable(DSS_CLK_ICK \| DSS_CLK_FCK1);		dss_clk_disable(DSS_CLK_ICK \| DSS_CLK_FCK);
	}		}

	bool dispc_go_busy(enum omap_channel channel)		bool dispc_go_busy(enum omap_channel channel)
	@@ -2311,7 +2311,7 @@ unsigned long dispc_fclk_rate(void)
	unsigned long r = 0;		unsigned long r = 0;

	if (dss_get_dispc_clk_source() == DSS_SRC_DSS1_ALWON_FCLK)		if (dss_get_dispc_clk_source() == DSS_SRC_DSS1_ALWON_FCLK)
	r = dss_clk_get_rate(DSS_CLK_FCK1);		r = dss_clk_get_rate(DSS_CLK_FCK);
	else		else
	#ifdef CONFIG_OMAP2_DSS_DSI		#ifdef CONFIG_OMAP2_DSS_DSI
	r = dsi_get_dsi1_pll_rate();		r = dsi_get_dsi1_pll_rate();
	@@ -2439,7 +2439,7 @@ void dispc_dump_regs(struct seq_file *s)
	{		{
	#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dispc_read_reg(r))		#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dispc_read_reg(r))

	dss_clk_enable(DSS_CLK_ICK \| DSS_CLK_FCK1);		dss_clk_enable(DSS_CLK_ICK \| DSS_CLK_FCK);

	DUMPREG(DISPC_REVISION);		DUMPREG(DISPC_REVISION);
	DUMPREG(DISPC_SYSCONFIG);		DUMPREG(DISPC_SYSCONFIG);
	@@ -2596,7 +2596,7 @@ void dispc_dump_regs(struct seq_file *s)
	DUMPREG(DISPC_VID_PRELOAD(0));		DUMPREG(DISPC_VID_PRELOAD(0));
	DUMPREG(DISPC_VID_PRELOAD(1));		DUMPREG(DISPC_VID_PRELOAD(1));

	dss_clk_disable(DSS_CLK_ICK \| DSS_CLK_FCK1);		dss_clk_disable(DSS_CLK_ICK \| DSS_CLK_FCK);
	#undef DUMPREG		#undef DUMPREG
	}		}

drivers/video/omap2/dss/dpi.c

+8 −8

Original line number	Original line	Diff line number	Diff line
	@@ -107,7 +107,7 @@ static int dpi_set_mode(struct omap_dss_device *dssdev)
	bool is_tft;		bool is_tft;
	int r = 0;		int r = 0;

	dss_clk_enable(DSS_CLK_ICK \| DSS_CLK_FCK1);		dss_clk_enable(DSS_CLK_ICK \| DSS_CLK_FCK);

	dispc_set_pol_freq(dssdev->manager->id, dssdev->panel.config,		dispc_set_pol_freq(dssdev->manager->id, dssdev->panel.config,
	dssdev->panel.acbi, dssdev->panel.acb);		dssdev->panel.acbi, dssdev->panel.acb);
	@@ -137,7 +137,7 @@ static int dpi_set_mode(struct omap_dss_device *dssdev)
	dispc_set_lcd_timings(dssdev->manager->id, t);		dispc_set_lcd_timings(dssdev->manager->id, t);

	err0:		err0:
	dss_clk_disable(DSS_CLK_ICK \| DSS_CLK_FCK1);		dss_clk_disable(DSS_CLK_ICK \| DSS_CLK_FCK);
	return r;		return r;
	}		}

	@@ -173,14 +173,14 @@ int omapdss_dpi_display_enable(struct omap_dss_device *dssdev)
	goto err1;		goto err1;
	}		}

	dss_clk_enable(DSS_CLK_ICK \| DSS_CLK_FCK1);		dss_clk_enable(DSS_CLK_ICK \| DSS_CLK_FCK);

	r = dpi_basic_init(dssdev);		r = dpi_basic_init(dssdev);
	if (r)		if (r)
	goto err2;		goto err2;

	#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL		#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
	dss_clk_enable(DSS_CLK_FCK2);		dss_clk_enable(DSS_CLK_SYSCK);
	r = dsi_pll_init(dssdev, 0, 1);		r = dsi_pll_init(dssdev, 0, 1);
	if (r)		if (r)
	goto err3;		goto err3;
	@@ -199,10 +199,10 @@ err4:
	#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL		#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
	dsi_pll_uninit();		dsi_pll_uninit();
	err3:		err3:
	dss_clk_disable(DSS_CLK_FCK2);		dss_clk_disable(DSS_CLK_SYSCK);
	#endif		#endif
	err2:		err2:
	dss_clk_disable(DSS_CLK_ICK \| DSS_CLK_FCK1);		dss_clk_disable(DSS_CLK_ICK \| DSS_CLK_FCK);
	if (cpu_is_omap34xx())		if (cpu_is_omap34xx())
	regulator_disable(dpi.vdds_dsi_reg);		regulator_disable(dpi.vdds_dsi_reg);
	err1:		err1:
	@@ -219,10 +219,10 @@ void omapdss_dpi_display_disable(struct omap_dss_device *dssdev)
	#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL		#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
	dss_select_dispc_clk_source(DSS_SRC_DSS1_ALWON_FCLK);		dss_select_dispc_clk_source(DSS_SRC_DSS1_ALWON_FCLK);
	dsi_pll_uninit();		dsi_pll_uninit();
	dss_clk_disable(DSS_CLK_FCK2);		dss_clk_disable(DSS_CLK_SYSCK);
	#endif		#endif

	dss_clk_disable(DSS_CLK_ICK \| DSS_CLK_FCK1);		dss_clk_disable(DSS_CLK_ICK \| DSS_CLK_FCK);

	if (cpu_is_omap34xx())		if (cpu_is_omap34xx())
	regulator_disable(dpi.vdds_dsi_reg);		regulator_disable(dpi.vdds_dsi_reg);

drivers/video/omap2/dss/dsi.c

+9 −9

Original line number	Original line	Diff line number	Diff line
	@@ -654,18 +654,18 @@ static void dsi_vc_disable_bta_irq(int channel)
	static inline void enable_clocks(bool enable)		static inline void enable_clocks(bool enable)
	{		{
	if (enable)		if (enable)
	dss_clk_enable(DSS_CLK_ICK \| DSS_CLK_FCK1);		dss_clk_enable(DSS_CLK_ICK \| DSS_CLK_FCK);
	else		else
	dss_clk_disable(DSS_CLK_ICK \| DSS_CLK_FCK1);		dss_clk_disable(DSS_CLK_ICK \| DSS_CLK_FCK);
	}		}

	/* source clock for DSI PLL. this could also be PCLKFREE */		/* source clock for DSI PLL. this could also be PCLKFREE */
	static inline void dsi_enable_pll_clock(bool enable)		static inline void dsi_enable_pll_clock(bool enable)
	{		{
	if (enable)		if (enable)
	dss_clk_enable(DSS_CLK_FCK2);		dss_clk_enable(DSS_CLK_SYSCK);
	else		else
	dss_clk_disable(DSS_CLK_FCK2);		dss_clk_disable(DSS_CLK_SYSCK);

	if (enable && dsi.pll_locked) {		if (enable && dsi.pll_locked) {
	if (wait_for_bit_change(DSI_PLL_STATUS, 1, 1) != 1)		if (wait_for_bit_change(DSI_PLL_STATUS, 1, 1) != 1)
	@@ -741,7 +741,7 @@ static unsigned long dsi_fclk_rate(void)

	if (dss_get_dsi_clk_source() == DSS_SRC_DSS1_ALWON_FCLK) {		if (dss_get_dsi_clk_source() == DSS_SRC_DSS1_ALWON_FCLK) {
	/* DSI FCLK source is DSS1_ALWON_FCK, which is dss1_fck */		/* DSI FCLK source is DSS1_ALWON_FCK, which is dss1_fck */
	r = dss_clk_get_rate(DSS_CLK_FCK1);		r = dss_clk_get_rate(DSS_CLK_FCK);
	} else {		} else {
	/* DSI FCLK source is DSI2_PLL_FCLK */		/* DSI FCLK source is DSI2_PLL_FCLK */
	r = dsi_get_dsi2_pll_rate();		r = dsi_get_dsi2_pll_rate();
	@@ -821,7 +821,7 @@ static int dsi_calc_clock_rates(struct omap_dss_device *dssdev,
	return -EINVAL;		return -EINVAL;

	if (cinfo->use_dss2_fck) {		if (cinfo->use_dss2_fck) {
	cinfo->clkin = dss_clk_get_rate(DSS_CLK_FCK2);		cinfo->clkin = dss_clk_get_rate(DSS_CLK_SYSCK);
	/* XXX it is unclear if highfreq should be used		/* XXX it is unclear if highfreq should be used
	* with DSS2_FCK source also */		* with DSS2_FCK source also */
	cinfo->highfreq = 0;		cinfo->highfreq = 0;
	@@ -867,7 +867,7 @@ int dsi_pll_calc_clock_div_pck(bool is_tft, unsigned long req_pck,
	int match = 0;		int match = 0;
	unsigned long dss_clk_fck2;		unsigned long dss_clk_fck2;

	dss_clk_fck2 = dss_clk_get_rate(DSS_CLK_FCK2);		dss_clk_fck2 = dss_clk_get_rate(DSS_CLK_SYSCK);

	if (req_pck == dsi.cache_req_pck &&		if (req_pck == dsi.cache_req_pck &&
	dsi.cache_cinfo.clkin == dss_clk_fck2) {		dsi.cache_cinfo.clkin == dss_clk_fck2) {
	@@ -1319,7 +1319,7 @@ void dsi_dump_regs(struct seq_file *s)
	{		{
	#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(r))		#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(r))

	dss_clk_enable(DSS_CLK_ICK \| DSS_CLK_FCK1);		dss_clk_enable(DSS_CLK_ICK \| DSS_CLK_FCK);

	DUMPREG(DSI_REVISION);		DUMPREG(DSI_REVISION);
	DUMPREG(DSI_SYSCONFIG);		DUMPREG(DSI_SYSCONFIG);
	@@ -1391,7 +1391,7 @@ void dsi_dump_regs(struct seq_file *s)
	DUMPREG(DSI_PLL_CONFIGURATION1);		DUMPREG(DSI_PLL_CONFIGURATION1);
	DUMPREG(DSI_PLL_CONFIGURATION2);		DUMPREG(DSI_PLL_CONFIGURATION2);

	dss_clk_disable(DSS_CLK_ICK \| DSS_CLK_FCK1);		dss_clk_disable(DSS_CLK_ICK \| DSS_CLK_FCK);
	#undef DUMPREG		#undef DUMPREG
	}		}

drivers/video/omap2/dss/dss.c

+31 −31

Original line number	Original line	Diff line number	Diff line
	@@ -227,7 +227,7 @@ void dss_dump_clocks(struct seq_file *s)
	unsigned long dpll4_ck_rate;		unsigned long dpll4_ck_rate;
	unsigned long dpll4_m4_ck_rate;		unsigned long dpll4_m4_ck_rate;

	dss_clk_enable(DSS_CLK_ICK \| DSS_CLK_FCK1);		dss_clk_enable(DSS_CLK_ICK \| DSS_CLK_FCK);

	dpll4_ck_rate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));		dpll4_ck_rate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
	dpll4_m4_ck_rate = clk_get_rate(dss.dpll4_m4_ck);		dpll4_m4_ck_rate = clk_get_rate(dss.dpll4_m4_ck);
	@@ -240,21 +240,21 @@ void dss_dump_clocks(struct seq_file *s)
	seq_printf(s, "dss1_alwon_fclk = %lu / %lu = %lu\n",		seq_printf(s, "dss1_alwon_fclk = %lu / %lu = %lu\n",
	dpll4_ck_rate,		dpll4_ck_rate,
	dpll4_ck_rate / dpll4_m4_ck_rate,		dpll4_ck_rate / dpll4_m4_ck_rate,
	dss_clk_get_rate(DSS_CLK_FCK1));		dss_clk_get_rate(DSS_CLK_FCK));
	else		else
	seq_printf(s, "dss1_alwon_fclk = %lu / %lu * 2 = %lu\n",		seq_printf(s, "dss1_alwon_fclk = %lu / %lu * 2 = %lu\n",
	dpll4_ck_rate,		dpll4_ck_rate,
	dpll4_ck_rate / dpll4_m4_ck_rate,		dpll4_ck_rate / dpll4_m4_ck_rate,
	dss_clk_get_rate(DSS_CLK_FCK1));		dss_clk_get_rate(DSS_CLK_FCK));

	dss_clk_disable(DSS_CLK_ICK \| DSS_CLK_FCK1);		dss_clk_disable(DSS_CLK_ICK \| DSS_CLK_FCK);
	}		}

	void dss_dump_regs(struct seq_file *s)		void dss_dump_regs(struct seq_file *s)
	{		{
	#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dss_read_reg(r))		#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dss_read_reg(r))

	dss_clk_enable(DSS_CLK_ICK \| DSS_CLK_FCK1);		dss_clk_enable(DSS_CLK_ICK \| DSS_CLK_FCK);

	DUMPREG(DSS_REVISION);		DUMPREG(DSS_REVISION);
	DUMPREG(DSS_SYSCONFIG);		DUMPREG(DSS_SYSCONFIG);
	@@ -265,7 +265,7 @@ void dss_dump_regs(struct seq_file *s)
	DUMPREG(DSS_PLL_CONTROL);		DUMPREG(DSS_PLL_CONTROL);
	DUMPREG(DSS_SDI_STATUS);		DUMPREG(DSS_SDI_STATUS);

	dss_clk_disable(DSS_CLK_ICK \| DSS_CLK_FCK1);		dss_clk_disable(DSS_CLK_ICK \| DSS_CLK_FCK);
	#undef DUMPREG		#undef DUMPREG
	}		}

	@@ -350,7 +350,7 @@ int dss_set_clock_div(struct dss_clock_info *cinfo)

	int dss_get_clock_div(struct dss_clock_info *cinfo)		int dss_get_clock_div(struct dss_clock_info *cinfo)
	{		{
	cinfo->fck = dss_clk_get_rate(DSS_CLK_FCK1);		cinfo->fck = dss_clk_get_rate(DSS_CLK_FCK);

	if (cpu_is_omap34xx()) {		if (cpu_is_omap34xx()) {
	unsigned long prate;		unsigned long prate;
	@@ -391,7 +391,7 @@ int dss_calc_clock_div(bool is_tft, unsigned long req_pck,

	prate = dss_get_dpll4_rate();		prate = dss_get_dpll4_rate();

	fck = dss_clk_get_rate(DSS_CLK_FCK1);		fck = dss_clk_get_rate(DSS_CLK_FCK);
	if (req_pck == dss.cache_req_pck &&		if (req_pck == dss.cache_req_pck &&
	((cpu_is_omap34xx() && prate == dss.cache_prate) \|\|		((cpu_is_omap34xx() && prate == dss.cache_prate) \|\|
	dss.cache_dss_cinfo.fck == fck)) {		dss.cache_dss_cinfo.fck == fck)) {
	@@ -418,7 +418,7 @@ retry:
	if (cpu_is_omap24xx()) {		if (cpu_is_omap24xx()) {
	struct dispc_clock_info cur_dispc;		struct dispc_clock_info cur_dispc;
	/* XXX can we change the clock on omap2? */		/* XXX can we change the clock on omap2? */
	fck = dss_clk_get_rate(DSS_CLK_FCK1);		fck = dss_clk_get_rate(DSS_CLK_FCK);
	fck_div = 1;		fck_div = 1;

	dispc_find_clk_divs(is_tft, req_pck, fck, &cur_dispc);		dispc_find_clk_divs(is_tft, req_pck, fck, &cur_dispc);
	@@ -701,7 +701,7 @@ static void save_all_ctx(void)
	{		{
	DSSDBG("save context\n");		DSSDBG("save context\n");

	dss_clk_enable_no_ctx(DSS_CLK_ICK \| DSS_CLK_FCK1);		dss_clk_enable_no_ctx(DSS_CLK_ICK \| DSS_CLK_FCK);

	dss_save_context();		dss_save_context();
	dispc_save_context();		dispc_save_context();
	@@ -709,7 +709,7 @@ static void save_all_ctx(void)
	dsi_save_context();		dsi_save_context();
	#endif		#endif

	dss_clk_disable_no_ctx(DSS_CLK_ICK \| DSS_CLK_FCK1);		dss_clk_disable_no_ctx(DSS_CLK_ICK \| DSS_CLK_FCK);
	}		}

	static void restore_all_ctx(void)		static void restore_all_ctx(void)
	@@ -807,13 +807,13 @@ unsigned long dss_clk_get_rate(enum dss_clock clk)
	switch (clk) {		switch (clk) {
	case DSS_CLK_ICK:		case DSS_CLK_ICK:
	return clk_get_rate(dss.dss_ick);		return clk_get_rate(dss.dss_ick);
	case DSS_CLK_FCK1:		case DSS_CLK_FCK:
	return clk_get_rate(dss.dss1_fck);		return clk_get_rate(dss.dss1_fck);
	case DSS_CLK_FCK2:		case DSS_CLK_SYSCK:
	return clk_get_rate(dss.dss2_fck);		return clk_get_rate(dss.dss2_fck);
	case DSS_CLK_54M:		case DSS_CLK_TVFCK:
	return clk_get_rate(dss.dss_54m_fck);		return clk_get_rate(dss.dss_54m_fck);
	case DSS_CLK_96M:		case DSS_CLK_VIDFCK:
	return clk_get_rate(dss.dss_96m_fck);		return clk_get_rate(dss.dss_96m_fck);
	}		}

	@@ -827,13 +827,13 @@ static unsigned count_clk_bits(enum dss_clock clks)

	if (clks & DSS_CLK_ICK)		if (clks & DSS_CLK_ICK)
	++num_clks;		++num_clks;
	if (clks & DSS_CLK_FCK1)		if (clks & DSS_CLK_FCK)
	++num_clks;		++num_clks;
	if (clks & DSS_CLK_FCK2)		if (clks & DSS_CLK_SYSCK)
	++num_clks;		++num_clks;
	if (clks & DSS_CLK_54M)		if (clks & DSS_CLK_TVFCK)
	++num_clks;		++num_clks;
	if (clks & DSS_CLK_96M)		if (clks & DSS_CLK_VIDFCK)
	++num_clks;		++num_clks;

	return num_clks;		return num_clks;
	@@ -845,13 +845,13 @@ static void dss_clk_enable_no_ctx(enum dss_clock clks)

	if (clks & DSS_CLK_ICK)		if (clks & DSS_CLK_ICK)
	clk_enable(dss.dss_ick);		clk_enable(dss.dss_ick);
	if (clks & DSS_CLK_FCK1)		if (clks & DSS_CLK_FCK)
	clk_enable(dss.dss1_fck);		clk_enable(dss.dss1_fck);
	if (clks & DSS_CLK_FCK2)		if (clks & DSS_CLK_SYSCK)
	clk_enable(dss.dss2_fck);		clk_enable(dss.dss2_fck);
	if (clks & DSS_CLK_54M)		if (clks & DSS_CLK_TVFCK)
	clk_enable(dss.dss_54m_fck);		clk_enable(dss.dss_54m_fck);
	if (clks & DSS_CLK_96M)		if (clks & DSS_CLK_VIDFCK)
	clk_enable(dss.dss_96m_fck);		clk_enable(dss.dss_96m_fck);

	dss.num_clks_enabled += num_clks;		dss.num_clks_enabled += num_clks;
	@@ -873,13 +873,13 @@ static void dss_clk_disable_no_ctx(enum dss_clock clks)

	if (clks & DSS_CLK_ICK)		if (clks & DSS_CLK_ICK)
	clk_disable(dss.dss_ick);		clk_disable(dss.dss_ick);
	if (clks & DSS_CLK_FCK1)		if (clks & DSS_CLK_FCK)
	clk_disable(dss.dss1_fck);		clk_disable(dss.dss1_fck);
	if (clks & DSS_CLK_FCK2)		if (clks & DSS_CLK_SYSCK)
	clk_disable(dss.dss2_fck);		clk_disable(dss.dss2_fck);
	if (clks & DSS_CLK_54M)		if (clks & DSS_CLK_TVFCK)
	clk_disable(dss.dss_54m_fck);		clk_disable(dss.dss_54m_fck);
	if (clks & DSS_CLK_96M)		if (clks & DSS_CLK_VIDFCK)
	clk_disable(dss.dss_96m_fck);		clk_disable(dss.dss_96m_fck);

	dss.num_clks_enabled -= num_clks;		dss.num_clks_enabled -= num_clks;
	@@ -903,9 +903,9 @@ static void dss_clk_enable_all_no_ctx(void)
	{		{
	enum dss_clock clks;		enum dss_clock clks;

	clks = DSS_CLK_ICK \| DSS_CLK_FCK1 \| DSS_CLK_FCK2 \| DSS_CLK_54M;		clks = DSS_CLK_ICK \| DSS_CLK_FCK \| DSS_CLK_SYSCK \| DSS_CLK_TVFCK;
	if (cpu_is_omap34xx())		if (cpu_is_omap34xx())
	clks \|= DSS_CLK_96M;		clks \|= DSS_CLK_VIDFCK;
	dss_clk_enable_no_ctx(clks);		dss_clk_enable_no_ctx(clks);
	}		}

	@@ -913,9 +913,9 @@ static void dss_clk_disable_all_no_ctx(void)
	{		{
	enum dss_clock clks;		enum dss_clock clks;

	clks = DSS_CLK_ICK \| DSS_CLK_FCK1 \| DSS_CLK_FCK2 \| DSS_CLK_54M;		clks = DSS_CLK_ICK \| DSS_CLK_FCK \| DSS_CLK_SYSCK \| DSS_CLK_TVFCK;
	if (cpu_is_omap34xx())		if (cpu_is_omap34xx())
	clks \|= DSS_CLK_96M;		clks \|= DSS_CLK_VIDFCK;
	dss_clk_disable_no_ctx(clks);		dss_clk_disable_no_ctx(clks);
	}		}