Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 6aedd1f5 authored by Paulo Zanoni's avatar Paulo Zanoni Committed by Daniel Vetter
Browse files

drm/i915: clarify Haswell power well bit names 



Whenever I need to work with the HSW_PWER_WELL_* register bits I have
to look at the documentation to find out which bit is to request the
power well and which one shows its current state. Rename the bits so I
won't need to look the docs every time.

Signed-off-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 8dc8a27c

drivers/gpu/drm/i915/i915_reg.h

+2 −2
Original line number Diff line number Diff line
@@ -4825,8 +4825,8 @@ 
#define HSW_PWR_WELL_DRIVER			0x45404 /* CTL2 */

#define HSW_PWR_WELL_KVMR			0x45408 /* CTL3 */

#define HSW_PWR_WELL_DEBUG			0x4540C /* CTL4 */

#define   HSW_PWR_WELL_ENABLE			(1<<31)

#define   HSW_PWR_WELL_STATE			(1<<30)

#define   HSW_PWR_WELL_ENABLE_REQUEST		(1<<31)

#define   HSW_PWR_WELL_STATE_ENABLED		(1<<30)

#define HSW_PWR_WELL_CTL5			0x45410

#define   HSW_PWR_WELL_ENABLE_SINGLE_STEP	(1<<31)

#define   HSW_PWR_WELL_PWR_GATE_OVERRIDE	(1<<20)

drivers/gpu/drm/i915/intel_display.c

+1 −1
Original line number Diff line number Diff line
@@ -10112,7 +10112,7 @@ void i915_redisable_vga(struct drm_device *dev) 
	 * follow the "don't touch the power well if we don't need it" policy

	 * the rest of the driver uses. */

	if (HAS_POWER_WELL(dev) &&

	    (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE) == 0)

	    (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0)

		return;



	if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {

drivers/gpu/drm/i915/intel_pm.c

+7 −6
Original line number Diff line number Diff line
@@ -5285,7 +5285,7 @@ bool intel_display_power_enabled(struct drm_device *dev, 
	case POWER_DOMAIN_TRANSCODER_B:

	case POWER_DOMAIN_TRANSCODER_C:

		return I915_READ(HSW_PWR_WELL_DRIVER) ==

		       (HSW_PWR_WELL_ENABLE | HSW_PWR_WELL_STATE);

		     (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);

	default:

		BUG();

	}
@@ -5298,17 +5298,18 @@ static void __intel_set_power_well(struct drm_device *dev, bool enable) 
	uint32_t tmp;



	tmp = I915_READ(HSW_PWR_WELL_DRIVER);

	is_enabled = tmp & HSW_PWR_WELL_STATE;

	enable_requested = tmp & HSW_PWR_WELL_ENABLE;

	is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;

	enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;



	if (enable) {

		if (!enable_requested)

			I915_WRITE(HSW_PWR_WELL_DRIVER, HSW_PWR_WELL_ENABLE);

			I915_WRITE(HSW_PWR_WELL_DRIVER,

				   HSW_PWR_WELL_ENABLE_REQUEST);



		if (!is_enabled) {

			DRM_DEBUG_KMS("Enabling power well\n");

			if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &

				      HSW_PWR_WELL_STATE), 20))

				      HSW_PWR_WELL_STATE_ENABLED), 20))

				DRM_ERROR("Timeout enabling power well\n");

		}

	} else {
@@ -5410,7 +5411,7 @@ void intel_init_power_well(struct drm_device *dev) 


	/* We're taking over the BIOS, so clear any requests made by it since

	 * the driver is in charge now. */

	if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE)

	if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)

		I915_WRITE(HSW_PWR_WELL_BIOS, 0);

}