Loading drivers/clk/msm/clock-local2.c +11 −3 Original line number Diff line number Diff line Loading @@ -1023,18 +1023,20 @@ unsigned long measure_get_rate(struct clk *c) u64 raw_count_short, raw_count_full; unsigned ret; u32 sample_ticks = 0x10000; u32 multiplier = 0x1; u32 multiplier = to_mux_clk(c)->post_div + 1; struct measure_clk_data *data = to_mux_clk(c)->priv; regval = readl_relaxed(MUX_REG(to_mux_clk(c))); /* clear post divider bits */ /* clear and set post divider bits */ regval &= ~BM(15, 12); regval |= BVAL(15, 12, to_mux_clk(c)->post_div); writel_relaxed(regval, MUX_REG(to_mux_clk(c))); ret = clk_prepare_enable(data->cxo); if (ret) { pr_warn("CXO clock failed to enable. Can't measure\n"); return 0; ret = 0; goto fail; } spin_lock_irqsave(&local_clock_reg_lock, flags); Loading Loading @@ -1076,6 +1078,12 @@ unsigned long measure_get_rate(struct clk *c) clk_disable_unprepare(data->cxo); fail: regval = readl_relaxed(MUX_REG(to_mux_clk(c))); /* clear post divider bits */ regval &= ~BM(15, 12); writel_relaxed(regval, MUX_REG(to_mux_clk(c))); return ret; } Loading include/linux/clk/msm-clock-generic.h +6 −1 Original line number Diff line number Diff line /* * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and Loading Loading @@ -81,6 +81,11 @@ struct mux_clk { u32 mask; u32 shift; u32 en_mask; /* * Set post divider for debug mux in order to divide the clock * by post_div + 1. */ u32 post_div; int low_power_sel; void *priv; Loading Loading
drivers/clk/msm/clock-local2.c +11 −3 Original line number Diff line number Diff line Loading @@ -1023,18 +1023,20 @@ unsigned long measure_get_rate(struct clk *c) u64 raw_count_short, raw_count_full; unsigned ret; u32 sample_ticks = 0x10000; u32 multiplier = 0x1; u32 multiplier = to_mux_clk(c)->post_div + 1; struct measure_clk_data *data = to_mux_clk(c)->priv; regval = readl_relaxed(MUX_REG(to_mux_clk(c))); /* clear post divider bits */ /* clear and set post divider bits */ regval &= ~BM(15, 12); regval |= BVAL(15, 12, to_mux_clk(c)->post_div); writel_relaxed(regval, MUX_REG(to_mux_clk(c))); ret = clk_prepare_enable(data->cxo); if (ret) { pr_warn("CXO clock failed to enable. Can't measure\n"); return 0; ret = 0; goto fail; } spin_lock_irqsave(&local_clock_reg_lock, flags); Loading Loading @@ -1076,6 +1078,12 @@ unsigned long measure_get_rate(struct clk *c) clk_disable_unprepare(data->cxo); fail: regval = readl_relaxed(MUX_REG(to_mux_clk(c))); /* clear post divider bits */ regval &= ~BM(15, 12); writel_relaxed(regval, MUX_REG(to_mux_clk(c))); return ret; } Loading
include/linux/clk/msm-clock-generic.h +6 −1 Original line number Diff line number Diff line /* * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and Loading Loading @@ -81,6 +81,11 @@ struct mux_clk { u32 mask; u32 shift; u32 en_mask; /* * Set post divider for debug mux in order to divide the clock * by post_div + 1. */ u32 post_div; int low_power_sel; void *priv; Loading