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Commit 6aa2e455 authored by Tarun Karra's avatar Tarun Karra Committed by Oleg Perelet
Browse files

msm: kgsl: Add support for the A540 GPU 



Add support for the A540 GPU device:
   * Add entry to the GPU list and add adreno_is_a540() functions
   * Add VBIF settings
   * Add hardware clock gating values

Change-Id: Ibd653597400ded01ca05607fbbdafea3e86e177f
Signed-off-by: default avatarTarun Karra <tkarra@codeaurora.org>
Signed-off-by: default avatarOleg Perelet <operelet@codeaurora.org>
parent cbac2b43

drivers/gpu/msm/a5xx_reg.h

+3 −0
Original line number Diff line number Diff line
@@ -290,6 +290,9 @@ 
#define A5XX_RBBM_CLOCK_HYST3_TP1                0xB9

#define A5XX_RBBM_CLOCK_HYST3_TP2                0xBA

#define A5XX_RBBM_CLOCK_HYST3_TP3                0xBB

#define A5XX_RBBM_CLOCK_CNTL_GPMU                0xC8

#define A5XX_RBBM_CLOCK_DELAY_GPMU               0xC9

#define A5XX_RBBM_CLOCK_HYST_GPMU                0xCA

#define A5XX_RBBM_PERFCTR_CP_0_LO                0x3A0

#define A5XX_RBBM_PERFCTR_CP_0_HI                0x3A1

#define A5XX_RBBM_PERFCTR_CP_1_LO                0x3A2

drivers/gpu/msm/adreno-gpulist.h

+16 −0
Original line number Diff line number Diff line
@@ -237,4 +237,20 @@ static const struct adreno_gpu_core adreno_gpulist[] = { 
		.num_protected_regs = 0x20,

		.busy_mask = 0xFFFFFFFE,

	},

	{

		.gpurev = ADRENO_REV_A540,

		.core = 5,

		.major = 4,

		.minor = 0,

		.patchid = ANY_ID,

		.features = ADRENO_PREEMPTION | ADRENO_64BIT |

			ADRENO_CONTENT_PROTECTION,

		.pm4fw_name = "a530_pm4.fw",

		.pfpfw_name = "a530_pfp.fw",

		.zap_name = "a530_zap",

		.gpudev = &adreno_a5xx_gpudev,

		.gmem_size = SZ_1M,

		.num_protected_regs = 0x20,

		.busy_mask = 0xFFFFFFFE,

	},

};

drivers/gpu/msm/adreno.h

+8 −0
Original line number Diff line number Diff line
@@ -170,6 +170,7 @@ enum adreno_gpurev { 
	ADRENO_REV_A506 = 506,

	ADRENO_REV_A510 = 510,

	ADRENO_REV_A530 = 530,

	ADRENO_REV_A540 = 540,

};



#define ADRENO_START_WARM 0
@@ -945,6 +946,7 @@ ADRENO_TARGET(a505, ADRENO_REV_A505) 
ADRENO_TARGET(a506, ADRENO_REV_A506)

ADRENO_TARGET(a510, ADRENO_REV_A510)

ADRENO_TARGET(a530, ADRENO_REV_A530)

ADRENO_TARGET(a540, ADRENO_REV_A540)



static inline int adreno_is_a530v1(struct adreno_device *adreno_dev)

{
@@ -969,6 +971,12 @@ static inline int adreno_is_a505_or_a506(struct adreno_device *adreno_dev) 
	return ADRENO_GPUREV(adreno_dev) >= 505 &&

			ADRENO_GPUREV(adreno_dev) <= 506;

}



static inline int adreno_is_a540v1(struct adreno_device *adreno_dev)

{

	return (ADRENO_GPUREV(adreno_dev) == ADRENO_REV_A540) &&

		(ADRENO_CHIPID_PATCH(adreno_dev->chipid) == 0);

}

/**

 * adreno_context_timestamp() - Return the last queued timestamp for the context

 * @k_ctxt: Pointer to the KGSL context to query

drivers/gpu/msm/adreno_a5xx.c

+118 −12
Original line number Diff line number Diff line
@@ -37,7 +37,14 @@ static const struct adreno_vbif_data a530_vbif[] = { 
	{0, 0},

};



static const struct adreno_vbif_data a540_vbif[] = {

	{A5XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x00000003},

	{A5XX_VBIF_GATE_OFF_WRREQ_EN, 0x00000009},

	{0, 0},

};



static const struct adreno_vbif_platform a5xx_vbif_platforms[] = {

	{ adreno_is_a540, a540_vbif },

	{ adreno_is_a530, a530_vbif },

	{ adreno_is_a510, a530_vbif },

	{ adreno_is_a505, a530_vbif },
@@ -445,7 +452,7 @@ static void a5xx_platform_setup(struct adreno_device *adreno_dev) 


static void a5xx_init(struct adreno_device *adreno_dev)

{

	if (adreno_is_a530(adreno_dev) && !adreno_is_a530v1(adreno_dev))

	if (ADRENO_FEATURE(adreno_dev, ADRENO_GPMU))

		INIT_WORK(&adreno_dev->gpmu_work, a5xx_gpmu_reset);



	a5xx_crashdump_init(adreno_dev);
@@ -562,7 +569,7 @@ static int a5xx_regulator_enable(struct adreno_device *adreno_dev) 
{

	unsigned int ret;

	struct kgsl_device *device = &adreno_dev->dev;

	if (!adreno_is_a530(adreno_dev))

	if (!(adreno_is_a530(adreno_dev) || adreno_is_a540(adreno_dev)))

		return 0;



	/*
@@ -833,9 +840,10 @@ static int a5xx_gpmu_start(struct adreno_device *adreno_dev) 
		return ret;

	}



	if (adreno_is_a530(adreno_dev)) {

		/* GPMU clock gating setup */

		kgsl_regwrite(device, A5XX_GPMU_WFI_CONFIG, 0x00004014);



	}

	/* Kick off GPMU firmware */

	kgsl_regwrite(device, A5XX_GPMU_CM3_SYSRESET, 0);

	/*
@@ -1066,11 +1074,111 @@ static const struct kgsl_hwcg_reg a530_hwcg_regs[] = { 
	{A5XX_RBBM_CLOCK_DELAY_VFD, 0x00002222}

};





static const struct kgsl_hwcg_reg a540_hwcg_regs[] = {

	{A5XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},

	{A5XX_RBBM_CLOCK_CNTL_SP1, 0x02222222},

	{A5XX_RBBM_CLOCK_CNTL_SP2, 0x02222222},

	{A5XX_RBBM_CLOCK_CNTL_SP3, 0x02222222},

	{A5XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},

	{A5XX_RBBM_CLOCK_CNTL2_SP1, 0x02222220},

	{A5XX_RBBM_CLOCK_CNTL2_SP2, 0x02222220},

	{A5XX_RBBM_CLOCK_CNTL2_SP3, 0x02222220},

	{A5XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},

	{A5XX_RBBM_CLOCK_HYST_SP1, 0x0000F3CF},

	{A5XX_RBBM_CLOCK_HYST_SP2, 0x0000F3CF},

	{A5XX_RBBM_CLOCK_HYST_SP3, 0x0000F3CF},

	{A5XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},

	{A5XX_RBBM_CLOCK_DELAY_SP1, 0x00000080},

	{A5XX_RBBM_CLOCK_DELAY_SP2, 0x00000080},

	{A5XX_RBBM_CLOCK_DELAY_SP3, 0x00000080},

	{A5XX_RBBM_CLOCK_CNTL_TP0, 0x22222222},

	{A5XX_RBBM_CLOCK_CNTL_TP1, 0x22222222},

	{A5XX_RBBM_CLOCK_CNTL_TP2, 0x22222222},

	{A5XX_RBBM_CLOCK_CNTL_TP3, 0x22222222},

	{A5XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},

	{A5XX_RBBM_CLOCK_CNTL2_TP1, 0x22222222},

	{A5XX_RBBM_CLOCK_CNTL2_TP2, 0x22222222},

	{A5XX_RBBM_CLOCK_CNTL2_TP3, 0x22222222},

	{A5XX_RBBM_CLOCK_CNTL3_TP0, 0x00002222},

	{A5XX_RBBM_CLOCK_CNTL3_TP1, 0x00002222},

	{A5XX_RBBM_CLOCK_CNTL3_TP2, 0x00002222},

	{A5XX_RBBM_CLOCK_CNTL3_TP3, 0x00002222},

	{A5XX_RBBM_CLOCK_HYST_TP0, 0x77777777},

	{A5XX_RBBM_CLOCK_HYST_TP1, 0x77777777},

	{A5XX_RBBM_CLOCK_HYST_TP2, 0x77777777},

	{A5XX_RBBM_CLOCK_HYST_TP3, 0x77777777},

	{A5XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},

	{A5XX_RBBM_CLOCK_HYST2_TP1, 0x77777777},

	{A5XX_RBBM_CLOCK_HYST2_TP2, 0x77777777},

	{A5XX_RBBM_CLOCK_HYST2_TP3, 0x77777777},

	{A5XX_RBBM_CLOCK_HYST3_TP0, 0x00007777},

	{A5XX_RBBM_CLOCK_HYST3_TP1, 0x00007777},

	{A5XX_RBBM_CLOCK_HYST3_TP2, 0x00007777},

	{A5XX_RBBM_CLOCK_HYST3_TP3, 0x00007777},

	{A5XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},

	{A5XX_RBBM_CLOCK_DELAY_TP1, 0x11111111},

	{A5XX_RBBM_CLOCK_DELAY_TP2, 0x11111111},

	{A5XX_RBBM_CLOCK_DELAY_TP3, 0x11111111},

	{A5XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},

	{A5XX_RBBM_CLOCK_DELAY2_TP1, 0x11111111},

	{A5XX_RBBM_CLOCK_DELAY2_TP2, 0x11111111},

	{A5XX_RBBM_CLOCK_DELAY2_TP3, 0x11111111},

	{A5XX_RBBM_CLOCK_DELAY3_TP0, 0x00001111},

	{A5XX_RBBM_CLOCK_DELAY3_TP1, 0x00001111},

	{A5XX_RBBM_CLOCK_DELAY3_TP2, 0x00001111},

	{A5XX_RBBM_CLOCK_DELAY3_TP3, 0x00001111},

	{A5XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},

	{A5XX_RBBM_CLOCK_CNTL2_UCHE, 0x22222222},

	{A5XX_RBBM_CLOCK_CNTL3_UCHE, 0x22222222},

	{A5XX_RBBM_CLOCK_CNTL4_UCHE, 0x00222222},

	{A5XX_RBBM_CLOCK_HYST_UCHE, 0x00444444},

	{A5XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},

	{A5XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},

	{A5XX_RBBM_CLOCK_CNTL_RB1, 0x22222222},

	{A5XX_RBBM_CLOCK_CNTL_RB2, 0x22222222},

	{A5XX_RBBM_CLOCK_CNTL_RB3, 0x22222222},

	{A5XX_RBBM_CLOCK_CNTL2_RB0, 0x00222222},

	{A5XX_RBBM_CLOCK_CNTL2_RB1, 0x00222222},

	{A5XX_RBBM_CLOCK_CNTL2_RB2, 0x00222222},

	{A5XX_RBBM_CLOCK_CNTL2_RB3, 0x00222222},

	{A5XX_RBBM_CLOCK_CNTL_CCU0, 0x00022220},

	{A5XX_RBBM_CLOCK_CNTL_CCU1, 0x00022220},

	{A5XX_RBBM_CLOCK_CNTL_CCU2, 0x00022220},

	{A5XX_RBBM_CLOCK_CNTL_CCU3, 0x00022220},

	{A5XX_RBBM_CLOCK_CNTL_RAC, 0x05522222},

	{A5XX_RBBM_CLOCK_CNTL2_RAC, 0x00555555},

	{A5XX_RBBM_CLOCK_HYST_RB_CCU0, 0x04040404},

	{A5XX_RBBM_CLOCK_HYST_RB_CCU1, 0x04040404},

	{A5XX_RBBM_CLOCK_HYST_RB_CCU2, 0x04040404},

	{A5XX_RBBM_CLOCK_HYST_RB_CCU3, 0x04040404},

	{A5XX_RBBM_CLOCK_HYST_RAC, 0x07444044},

	{A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_0, 0x00000002},

	{A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_1, 0x00000002},

	{A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_2, 0x00000002},

	{A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_3, 0x00000002},

	{A5XX_RBBM_CLOCK_DELAY_RAC, 0x00010011},

	{A5XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},

	{A5XX_RBBM_CLOCK_MODE_GPC, 0x02222222},

	{A5XX_RBBM_CLOCK_MODE_VFD, 0x00002222},

	{A5XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},

	{A5XX_RBBM_CLOCK_HYST_GPC, 0x04104004},

	{A5XX_RBBM_CLOCK_HYST_VFD, 0x00000000},

	{A5XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},

	{A5XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},

	{A5XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},

	{A5XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},

	{A5XX_RBBM_CLOCK_HYST_GPMU, 0x00000222},

	{A5XX_RBBM_CLOCK_DELAY_GPMU, 0x00000770},

	{A5XX_RBBM_CLOCK_HYST_GPMU, 0x00000004}

};



static const struct {

	int (*devfunc)(struct adreno_device *adreno_dev);

	const struct kgsl_hwcg_reg *regs;

	unsigned int count;

} a5xx_hwcg_registers[] = {

	{ adreno_is_a540, a540_hwcg_regs, ARRAY_SIZE(a540_hwcg_regs) },

	{ adreno_is_a530v3, a530_hwcg_regs, ARRAY_SIZE(a530_hwcg_regs) },

	{ adreno_is_a530v2, a530_hwcg_regs, ARRAY_SIZE(a530_hwcg_regs) },

	{ adreno_is_a510, a510_hwcg_regs, ARRAY_SIZE(a510_hwcg_regs) },
@@ -1369,7 +1477,6 @@ static void a5xx_lm_init(struct adreno_device *adreno_dev) 
 */

static void a5xx_lm_enable(struct adreno_device *adreno_dev)

{

	uint32_t val;

	struct kgsl_device *device = &adreno_dev->dev;



	if (!ADRENO_FEATURE(adreno_dev, ADRENO_LM) ||
@@ -1387,12 +1494,11 @@ static void a5xx_lm_enable(struct adreno_device *adreno_dev) 
			0x00050000);

	kgsl_regwrite(device, A5XX_GPMU_THROTTLE_UNMASK_FORCE_CTRL,

			0x00030000);

	if (adreno_is_a530v2(adreno_dev))

		val = 0x00060011;

	/* v3 value */

	else

		val = 0x00000011;

	kgsl_regwrite(device, A5XX_GPMU_CLOCK_THROTTLE_CTRL, val);



	if (adreno_is_a530(adreno_dev))

		/* Program throttle control, do not enable idle DCS on v3+ */

		kgsl_regwrite(device, A5XX_GPMU_CLOCK_THROTTLE_CTRL,

			adreno_is_a530v2(adreno_dev) ? 0x00060011 : 0x00000011);

}



static int gpmu_set_level(struct kgsl_device *device, unsigned int val)