Merge commit 'gcl/next' into next (6a4d7a90) · Commits · e / devices / android_kernel_xiaomi_markw

arch/powerpc/boot/Makefile

+3 −1

Original line number	Diff line number	Diff line
		@@ -235,7 +235,9 @@ image-$(CONFIG_PPC_ADDER875) += cuImage.adder875-uboot \
		dtbImage.adder875-redboot

		# Board ports in arch/powerpc/platform/52xx/Kconfig
		image-$(CONFIG_PPC_LITE5200) += cuImage.lite5200 cuImage.lite5200b
		image-$(CONFIG_PPC_LITE5200) += cuImage.lite5200 lite5200.dtb
		image-$(CONFIG_PPC_LITE5200) += cuImage.lite5200b lite5200b.dtb
		image-$(CONFIG_PPC_MEDIA5200) += cuImage.media5200 media5200.dtb

		# Board ports in arch/powerpc/platform/82xx/Kconfig
		image-$(CONFIG_MPC8272_ADS) += cuImage.mpc8272ads

arch/powerpc/boot/dts/cm5200.dts

+11 −38

Original line number	Diff line number	Diff line
		@@ -17,6 +17,7 @@
		compatible = "schindler,cm5200";
		#address-cells = <1>;
		#size-cells = <1>;
		interrupt-parent = <&mpc5200_pic>;

		cpus {
		#address-cells = <1>;
		@@ -66,7 +67,6 @@
		compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
		reg = <0x600 0x10>;
		interrupts = <1 9 0>;
		interrupt-parent = <&mpc5200_pic>;
		fsl,has-wdt;
		};

		@@ -74,84 +74,76 @@
		compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
		reg = <0x610 0x10>;
		interrupts = <1 10 0>;
		interrupt-parent = <&mpc5200_pic>;
		};

		timer@620 { // General Purpose Timer
		compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
		reg = <0x620 0x10>;
		interrupts = <1 11 0>;
		interrupt-parent = <&mpc5200_pic>;
		};

		timer@630 { // General Purpose Timer
		compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
		reg = <0x630 0x10>;
		interrupts = <1 12 0>;
		interrupt-parent = <&mpc5200_pic>;
		};

		timer@640 { // General Purpose Timer
		compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
		reg = <0x640 0x10>;
		interrupts = <1 13 0>;
		interrupt-parent = <&mpc5200_pic>;
		};

		timer@650 { // General Purpose Timer
		compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
		reg = <0x650 0x10>;
		interrupts = <1 14 0>;
		interrupt-parent = <&mpc5200_pic>;
		};

		timer@660 { // General Purpose Timer
		compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
		reg = <0x660 0x10>;
		interrupts = <1 15 0>;
		interrupt-parent = <&mpc5200_pic>;
		};

		timer@670 { // General Purpose Timer
		compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
		reg = <0x670 0x10>;
		interrupts = <1 16 0>;
		interrupt-parent = <&mpc5200_pic>;
		};

		rtc@800 { // Real time clock
		compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
		reg = <0x800 0x100>;
		interrupts = <1 5 0 1 6 0>;
		interrupt-parent = <&mpc5200_pic>;
		};

		gpio@b00 {
		gpio_simple: gpio@b00 {
		compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
		reg = <0xb00 0x40>;
		interrupts = <1 7 0>;
		interrupt-parent = <&mpc5200_pic>;
		gpio-controller;
		#gpio-cells = <2>;
		};

		gpio@c00 {
		gpio_wkup: gpio@c00 {
		compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
		reg = <0xc00 0x40>;
		interrupts = <1 8 0 0 3 0>;
		interrupt-parent = <&mpc5200_pic>;
		gpio-controller;
		#gpio-cells = <2>;
		};

		spi@f00 {
		compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
		reg = <0xf00 0x20>;
		interrupts = <2 13 0 2 14 0>;
		interrupt-parent = <&mpc5200_pic>;
		};

		usb@1000 {
		compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
		reg = <0x1000 0xff>;
		interrupts = <2 6 0>;
		interrupt-parent = <&mpc5200_pic>;
		};

		dma-controller@1200 {
		@@ -161,7 +153,6 @@
		3 4 0 3 5 0 3 6 0 3 7 0
		3 8 0 3 9 0 3 10 0 3 11 0
		3 12 0 3 13 0 3 14 0 3 15 0>;
		interrupt-parent = <&mpc5200_pic>;
		};

		xlb@1f00 {
		@@ -170,48 +161,34 @@
		};

		serial@2000 { // PSC1
		device_type = "serial";
		compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
		port-number = <0>; // Logical port assignment
		reg = <0x2000 0x100>;
		interrupts = <2 1 0>;
		interrupt-parent = <&mpc5200_pic>;
		};

		serial@2200 { // PSC2
		device_type = "serial";
		compatible = "fsl,mpc5200-psc-uart";
		port-number = <1>; // Logical port assignment
		compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
		reg = <0x2200 0x100>;
		interrupts = <2 2 0>;
		interrupt-parent = <&mpc5200_pic>;
		};

		serial@2400 { // PSC3
		device_type = "serial";
		compatible = "fsl,mpc5200-psc-uart";
		port-number = <2>; // Logical port assignment
		compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
		reg = <0x2400 0x100>;
		interrupts = <2 3 0>;
		interrupt-parent = <&mpc5200_pic>;
		};

		serial@2c00 { // PSC6
		device_type = "serial";
		compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
		port-number = <5>; // Logical port assignment
		reg = <0x2c00 0x100>;
		interrupts = <2 4 0>;
		interrupt-parent = <&mpc5200_pic>;
		};

		ethernet@3000 {
		device_type = "network";
		compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
		reg = <0x3000 0x400>;
		local-mac-address = [ 00 00 00 00 00 00 ];
		interrupts = <2 5 0>;
		interrupt-parent = <&mpc5200_pic>;
		phy-handle = <&phy0>;
		};

		@@ -221,10 +198,8 @@
		compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
		reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
		interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
		interrupt-parent = <&mpc5200_pic>;

		phy0: ethernet-phy@0 {
		device_type = "ethernet-phy";
		reg = <0>;
		};
		};
		@@ -235,7 +210,6 @@
		compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
		reg = <0x3d40 0x40>;
		interrupts = <2 16 0>;
		interrupt-parent = <&mpc5200_pic>;
		fsl5200-clocking;
		};

		@@ -245,9 +219,8 @@
		};
		};

		lpb {
		model = "fsl,lpb";
		compatible = "fsl,lpb";
		localbus {
		compatible = "fsl,mpc5200b-lpb","simple-bus";
		#address-cells = <2>;
		#size-cells = <1>;
		ranges = <0 0 0xfc000000 0x2000000>;

arch/powerpc/boot/dts/digsy_mtc.dts

0 → 100644

+254 −0

Original line number	Diff line number	Diff line
		/*
		* Digsy MTC board Device Tree Source
		*
		* Copyright (C) 2009 Semihalf
		*
		* Based on the CM5200 by M. Balakowicz
		*
		* This program is free software; you can redistribute it and/or modify it
		* under the terms of the GNU General Public License as published by the
		* Free Software Foundation; either version 2 of the License, or (at your
		* option) any later version.
		*/

		/dts-v1/;

		/ {
		model = "intercontrol,digsy-mtc";
		compatible = "intercontrol,digsy-mtc";
		#address-cells = <1>;
		#size-cells = <1>;
		interrupt-parent = <&mpc5200_pic>;

		cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		PowerPC,5200@0 {
		device_type = "cpu";
		reg = <0>;
		d-cache-line-size = <32>;
		i-cache-line-size = <32>;
		d-cache-size = <0x4000>; // L1, 16K
		i-cache-size = <0x4000>; // L1, 16K
		timebase-frequency = <0>; // from bootloader
		bus-frequency = <0>; // from bootloader
		clock-frequency = <0>; // from bootloader
		};
		};

		memory {
		device_type = "memory";
		reg = <0x00000000 0x02000000>; // 32MB
		};

		soc5200@f0000000 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "fsl,mpc5200b-immr";
		ranges = <0 0xf0000000 0x0000c000>;
		reg = <0xf0000000 0x00000100>;
		bus-frequency = <0>; // from bootloader
		system-frequency = <0>; // from bootloader

		cdm@200 {
		compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
		reg = <0x200 0x38>;
		};

		mpc5200_pic: interrupt-controller@500 {
		// 5200 interrupts are encoded into two levels;
		interrupt-controller;
		#interrupt-cells = <3>;
		compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
		reg = <0x500 0x80>;
		};

		timer@600 { // General Purpose Timer
		compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
		reg = <0x600 0x10>;
		interrupts = <1 9 0>;
		fsl,has-wdt;
		};

		timer@610 { // General Purpose Timer
		compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
		reg = <0x610 0x10>;
		interrupts = <1 10 0>;
		};

		timer@620 { // General Purpose Timer
		compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
		reg = <0x620 0x10>;
		interrupts = <1 11 0>;
		};

		timer@630 { // General Purpose Timer
		compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
		reg = <0x630 0x10>;
		interrupts = <1 12 0>;
		};

		timer@640 { // General Purpose Timer
		compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
		reg = <0x640 0x10>;
		interrupts = <1 13 0>;
		};

		timer@650 { // General Purpose Timer
		compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
		reg = <0x650 0x10>;
		interrupts = <1 14 0>;
		};

		timer@660 { // General Purpose Timer
		compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
		reg = <0x660 0x10>;
		interrupts = <1 15 0>;
		};

		timer@670 { // General Purpose Timer
		compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
		reg = <0x670 0x10>;
		interrupts = <1 16 0>;
		};

		gpio_simple: gpio@b00 {
		compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
		reg = <0xb00 0x40>;
		interrupts = <1 7 0>;
		gpio-controller;
		#gpio-cells = <2>;
		};

		gpio_wkup: gpio@c00 {
		compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
		reg = <0xc00 0x40>;
		interrupts = <1 8 0 0 3 0>;
		gpio-controller;
		#gpio-cells = <2>;
		};

		spi@f00 {
		compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
		reg = <0xf00 0x20>;
		interrupts = <2 13 0 2 14 0>;
		};

		usb@1000 {
		compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
		reg = <0x1000 0xff>;
		interrupts = <2 6 0>;
		};

		dma-controller@1200 {
		compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
		reg = <0x1200 0x80>;
		interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
		3 4 0 3 5 0 3 6 0 3 7 0
		3 8 0 3 9 0 3 10 0 3 11 0
		3 12 0 3 13 0 3 14 0 3 15 0>;
		};

		xlb@1f00 {
		compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
		reg = <0x1f00 0x100>;
		};

		serial@2400 { // PSC3
		compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
		reg = <0x2400 0x100>;
		interrupts = <2 3 0>;
		};

		serial@2600 { // PSC4
		compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
		reg = <0x2600 0x100>;
		interrupts = <2 11 0>;
		};

		ethernet@3000 {
		compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
		reg = <0x3000 0x400>;
		local-mac-address = [ 00 00 00 00 00 00 ];
		interrupts = <2 5 0>;
		phy-handle = <&phy0>;
		};

		mdio@3000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
		reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
		interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.

		phy0: ethernet-phy@0 {
		reg = <0>;
		};
		};

		ata@3a00 {
		compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
		reg = <0x3a00 0x100>;
		interrupts = <2 7 0>;
		};

		i2c@3d00 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
		reg = <0x3d00 0x40>;
		interrupts = <2 15 0>;
		fsl5200-clocking;

		rtc@50 {
		compatible = "at,24c08";
		reg = <0x50>;
		};

		rtc@68 {
		compatible = "dallas,ds1339";
		reg = <0x68>;
		};
		};

		sram@8000 {
		compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
		reg = <0x8000 0x4000>;
		};
		};

		lpb {
		compatible = "fsl,mpc5200b-lpb","simple-bus";
		#address-cells = <2>;
		#size-cells = <1>;
		ranges = <0 0 0xff000000 0x1000000>;

		// 16-bit flash device at LocalPlus Bus CS0
		flash@0,0 {
		compatible = "cfi-flash";
		reg = <0 0 0x1000000>;
		bank-width = <2>;
		device-width = <2>;
		#size-cells = <1>;
		#address-cells = <1>;

		partition@0 {
		label = "kernel";
		reg = <0x0 0x00200000>;
		};
		partition@200000 {
		label = "root";
		reg = <0x00200000 0x00300000>;
		};
		partition@500000 {
		label = "user";
		reg = <0x00500000 0x00a00000>;
		};
		partition@f00000 {
		label = "u-boot";
		reg = <0x00f00000 0x100000>;
		};
		};
		};
		};

arch/powerpc/boot/dts/lite5200.dts

+2 −50

Original line number	Diff line number	Diff line
		@@ -17,6 +17,7 @@
		compatible = "fsl,lite5200";
		#address-cells = <1>;
		#size-cells = <1>;
		interrupt-parent = <&mpc5200_pic>;

		cpus {
		#address-cells = <1>;
		@@ -58,96 +59,74 @@
		// 5200 interrupts are encoded into two levels;
		interrupt-controller;
		#interrupt-cells = <3>;
		device_type = "interrupt-controller";
		compatible = "fsl,mpc5200-pic";
		reg = <0x500 0x80>;
		};

		timer@600 { // General Purpose Timer
		compatible = "fsl,mpc5200-gpt";
		cell-index = <0>;
		reg = <0x600 0x10>;
		interrupts = <1 9 0>;
		interrupt-parent = <&mpc5200_pic>;
		fsl,has-wdt;
		};

		timer@610 { // General Purpose Timer
		compatible = "fsl,mpc5200-gpt";
		cell-index = <1>;
		reg = <0x610 0x10>;
		interrupts = <1 10 0>;
		interrupt-parent = <&mpc5200_pic>;
		};

		timer@620 { // General Purpose Timer
		compatible = "fsl,mpc5200-gpt";
		cell-index = <2>;
		reg = <0x620 0x10>;
		interrupts = <1 11 0>;
		interrupt-parent = <&mpc5200_pic>;
		};

		timer@630 { // General Purpose Timer
		compatible = "fsl,mpc5200-gpt";
		cell-index = <3>;
		reg = <0x630 0x10>;
		interrupts = <1 12 0>;
		interrupt-parent = <&mpc5200_pic>;
		};

		timer@640 { // General Purpose Timer
		compatible = "fsl,mpc5200-gpt";
		cell-index = <4>;
		reg = <0x640 0x10>;
		interrupts = <1 13 0>;
		interrupt-parent = <&mpc5200_pic>;
		};

		timer@650 { // General Purpose Timer
		compatible = "fsl,mpc5200-gpt";
		cell-index = <5>;
		reg = <0x650 0x10>;
		interrupts = <1 14 0>;
		interrupt-parent = <&mpc5200_pic>;
		};

		timer@660 { // General Purpose Timer
		compatible = "fsl,mpc5200-gpt";
		cell-index = <6>;
		reg = <0x660 0x10>;
		interrupts = <1 15 0>;
		interrupt-parent = <&mpc5200_pic>;
		};

		timer@670 { // General Purpose Timer
		compatible = "fsl,mpc5200-gpt";
		cell-index = <7>;
		reg = <0x670 0x10>;
		interrupts = <1 16 0>;
		interrupt-parent = <&mpc5200_pic>;
		};

		rtc@800 { // Real time clock
		compatible = "fsl,mpc5200-rtc";
		reg = <0x800 0x100>;
		interrupts = <1 5 0 1 6 0>;
		interrupt-parent = <&mpc5200_pic>;
		};

		can@900 {
		compatible = "fsl,mpc5200-mscan";
		cell-index = <0>;
		interrupts = <2 17 0>;
		interrupt-parent = <&mpc5200_pic>;
		reg = <0x900 0x80>;
		};

		can@980 {
		compatible = "fsl,mpc5200-mscan";
		cell-index = <1>;
		interrupts = <2 18 0>;
		interrupt-parent = <&mpc5200_pic>;
		reg = <0x980 0x80>;
		};

		@@ -155,39 +134,33 @@
		compatible = "fsl,mpc5200-gpio";
		reg = <0xb00 0x40>;
		interrupts = <1 7 0>;
		interrupt-parent = <&mpc5200_pic>;
		};

		gpio@c00 {
		compatible = "fsl,mpc5200-gpio-wkup";
		reg = <0xc00 0x40>;
		interrupts = <1 8 0 0 3 0>;
		interrupt-parent = <&mpc5200_pic>;
		};

		spi@f00 {
		compatible = "fsl,mpc5200-spi";
		reg = <0xf00 0x20>;
		interrupts = <2 13 0 2 14 0>;
		interrupt-parent = <&mpc5200_pic>;
		};

		usb@1000 {
		compatible = "fsl,mpc5200-ohci","ohci-be";
		reg = <0x1000 0xff>;
		interrupts = <2 6 0>;
		interrupt-parent = <&mpc5200_pic>;
		};

		dma-controller@1200 {
		device_type = "dma-controller";
		compatible = "fsl,mpc5200-bestcomm";
		reg = <0x1200 0x80>;
		interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
		3 4 0 3 5 0 3 6 0 3 7 0
		3 8 0 3 9 0 3 10 0 3 11 0
		3 12 0 3 13 0 3 14 0 3 15 0>;
		interrupt-parent = <&mpc5200_pic>;
		};

		xlb@1f00 {
		@@ -196,13 +169,10 @@
		};

		serial@2000 { // PSC1
		device_type = "serial";
		compatible = "fsl,mpc5200-psc-uart";
		port-number = <0>; // Logical port assignment
		cell-index = <0>;
		reg = <0x2000 0x100>;
		interrupts = <2 1 0>;
		interrupt-parent = <&mpc5200_pic>;
		};

		// PSC2 in ac97 mode example
		@@ -211,7 +181,6 @@
		// cell-index = <1>;
		// reg = <0x2200 0x100>;
		// interrupts = <2 2 0>;
		// interrupt-parent = <&mpc5200_pic>;
		//};

		// PSC3 in CODEC mode example
		@@ -220,27 +189,22 @@
		// cell-index = <2>;
		// reg = <0x2400 0x100>;
		// interrupts = <2 3 0>;
		// interrupt-parent = <&mpc5200_pic>;
		//};

		// PSC4 in uart mode example
		//serial@2600 { // PSC4
		// device_type = "serial";
		// compatible = "fsl,mpc5200-psc-uart";
		// cell-index = <3>;
		// reg = <0x2600 0x100>;
		// interrupts = <2 11 0>;
		// interrupt-parent = <&mpc5200_pic>;
		//};

		// PSC5 in uart mode example
		//serial@2800 { // PSC5
		// device_type = "serial";
		// compatible = "fsl,mpc5200-psc-uart";
		// cell-index = <4>;
		// reg = <0x2800 0x100>;
		// interrupts = <2 12 0>;
		// interrupt-parent = <&mpc5200_pic>;
		//};

		// PSC6 in spi mode example
		@@ -249,16 +213,13 @@
		// cell-index = <5>;
		// reg = <0x2c00 0x100>;
		// interrupts = <2 4 0>;
		// interrupt-parent = <&mpc5200_pic>;
		//};

		ethernet@3000 {
		device_type = "network";
		compatible = "fsl,mpc5200-fec";
		reg = <0x3000 0x400>;
		local-mac-address = [ 00 00 00 00 00 00 ];
		interrupts = <2 5 0>;
		interrupt-parent = <&mpc5200_pic>;
		phy-handle = <&phy0>;
		};

		@@ -268,30 +229,24 @@
		compatible = "fsl,mpc5200-mdio";
		reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
		interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
		interrupt-parent = <&mpc5200_pic>;

		phy0: ethernet-phy@1 {
		device_type = "ethernet-phy";
		reg = <1>;
		};
		};

		ata@3a00 {
		device_type = "ata";
		compatible = "fsl,mpc5200-ata";
		reg = <0x3a00 0x100>;
		interrupts = <2 7 0>;
		interrupt-parent = <&mpc5200_pic>;
		};

		i2c@3d00 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "fsl,mpc5200-i2c","fsl-i2c";
		cell-index = <0>;
		reg = <0x3d00 0x40>;
		interrupts = <2 15 0>;
		interrupt-parent = <&mpc5200_pic>;
		fsl5200-clocking;
		};

		@@ -299,14 +254,12 @@
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "fsl,mpc5200-i2c","fsl-i2c";
		cell-index = <1>;
		reg = <0x3d40 0x40>;
		interrupts = <2 16 0>;
		interrupt-parent = <&mpc5200_pic>;
		fsl5200-clocking;
		};
		sram@8000 {
		compatible = "fsl,mpc5200-sram","sram";
		compatible = "fsl,mpc5200-sram";
		reg = <0x8000 0x4000>;
		};
		};
		@@ -325,7 +278,6 @@
		0xc000 0 0 4 &mpc5200_pic 0 0 3>;
		clock-frequency = <0>; // From boot loader
		interrupts = <2 8 0 2 9 0 2 10 0>;
		interrupt-parent = <&mpc5200_pic>;
		bus-range = <0 0>;
		ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000
		0x02000000 0 0xa0000000 0xa0000000 0 0x10000000

arch/powerpc/boot/dts/lite5200b.dts

+10 −53

Original line number	Diff line number	Diff line
		@@ -17,6 +17,7 @@
		compatible = "fsl,lite5200b";
		#address-cells = <1>;
		#size-cells = <1>;
		interrupt-parent = <&mpc5200_pic>;

		cpus {
		#address-cells = <1>;
		@@ -58,136 +59,112 @@
		// 5200 interrupts are encoded into two levels;
		interrupt-controller;
		#interrupt-cells = <3>;
		device_type = "interrupt-controller";
		compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
		reg = <0x500 0x80>;
		};

		timer@600 { // General Purpose Timer
		compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
		cell-index = <0>;
		reg = <0x600 0x10>;
		interrupts = <1 9 0>;
		interrupt-parent = <&mpc5200_pic>;
		fsl,has-wdt;
		};

		timer@610 { // General Purpose Timer
		compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
		cell-index = <1>;
		reg = <0x610 0x10>;
		interrupts = <1 10 0>;
		interrupt-parent = <&mpc5200_pic>;
		};

		timer@620 { // General Purpose Timer
		compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
		cell-index = <2>;
		reg = <0x620 0x10>;
		interrupts = <1 11 0>;
		interrupt-parent = <&mpc5200_pic>;
		};

		timer@630 { // General Purpose Timer
		compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
		cell-index = <3>;
		reg = <0x630 0x10>;
		interrupts = <1 12 0>;
		interrupt-parent = <&mpc5200_pic>;
		};

		timer@640 { // General Purpose Timer
		compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
		cell-index = <4>;
		reg = <0x640 0x10>;
		interrupts = <1 13 0>;
		interrupt-parent = <&mpc5200_pic>;
		};

		timer@650 { // General Purpose Timer
		compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
		cell-index = <5>;
		reg = <0x650 0x10>;
		interrupts = <1 14 0>;
		interrupt-parent = <&mpc5200_pic>;
		};

		timer@660 { // General Purpose Timer
		compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
		cell-index = <6>;
		reg = <0x660 0x10>;
		interrupts = <1 15 0>;
		interrupt-parent = <&mpc5200_pic>;
		};

		timer@670 { // General Purpose Timer
		compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
		cell-index = <7>;
		reg = <0x670 0x10>;
		interrupts = <1 16 0>;
		interrupt-parent = <&mpc5200_pic>;
		};

		rtc@800 { // Real time clock
		compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
		reg = <0x800 0x100>;
		interrupts = <1 5 0 1 6 0>;
		interrupt-parent = <&mpc5200_pic>;
		};

		can@900 {
		compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
		cell-index = <0>;
		interrupts = <2 17 0>;
		interrupt-parent = <&mpc5200_pic>;
		reg = <0x900 0x80>;
		};

		can@980 {
		compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
		cell-index = <1>;
		interrupts = <2 18 0>;
		interrupt-parent = <&mpc5200_pic>;
		reg = <0x980 0x80>;
		};

		gpio@b00 {
		gpio_simple: gpio@b00 {
		compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
		reg = <0xb00 0x40>;
		interrupts = <1 7 0>;
		interrupt-parent = <&mpc5200_pic>;
		gpio-controller;
		#gpio-cells = <2>;
		};

		gpio@c00 {
		gpio_wkup: gpio@c00 {
		compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
		reg = <0xc00 0x40>;
		interrupts = <1 8 0 0 3 0>;
		interrupt-parent = <&mpc5200_pic>;
		gpio-controller;
		#gpio-cells = <2>;
		};

		spi@f00 {
		compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
		reg = <0xf00 0x20>;
		interrupts = <2 13 0 2 14 0>;
		interrupt-parent = <&mpc5200_pic>;
		};

		usb@1000 {
		compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
		reg = <0x1000 0xff>;
		interrupts = <2 6 0>;
		interrupt-parent = <&mpc5200_pic>;
		};

		dma-controller@1200 {
		device_type = "dma-controller";
		compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
		reg = <0x1200 0x80>;
		interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
		3 4 0 3 5 0 3 6 0 3 7 0
		3 8 0 3 9 0 3 10 0 3 11 0
		3 12 0 3 13 0 3 14 0 3 15 0>;
		interrupt-parent = <&mpc5200_pic>;
		};

		xlb@1f00 {
		@@ -196,13 +173,10 @@
		};

		serial@2000 { // PSC1
		device_type = "serial";
		compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
		port-number = <0>; // Logical port assignment
		cell-index = <0>;
		reg = <0x2000 0x100>;
		interrupts = <2 1 0>;
		interrupt-parent = <&mpc5200_pic>;
		};

		// PSC2 in ac97 mode example
		@@ -211,7 +185,6 @@
		// cell-index = <1>;
		// reg = <0x2200 0x100>;
		// interrupts = <2 2 0>;
		// interrupt-parent = <&mpc5200_pic>;
		//};

		// PSC3 in CODEC mode example
		@@ -220,27 +193,22 @@
		// cell-index = <2>;
		// reg = <0x2400 0x100>;
		// interrupts = <2 3 0>;
		// interrupt-parent = <&mpc5200_pic>;
		//};

		// PSC4 in uart mode example
		//serial@2600 { // PSC4
		// device_type = "serial";
		// compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
		// cell-index = <3>;
		// reg = <0x2600 0x100>;
		// interrupts = <2 11 0>;
		// interrupt-parent = <&mpc5200_pic>;
		//};

		// PSC5 in uart mode example
		//serial@2800 { // PSC5
		// device_type = "serial";
		// compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
		// cell-index = <4>;
		// reg = <0x2800 0x100>;
		// interrupts = <2 12 0>;
		// interrupt-parent = <&mpc5200_pic>;
		//};

		// PSC6 in spi mode example
		@@ -249,16 +217,13 @@
		// cell-index = <5>;
		// reg = <0x2c00 0x100>;
		// interrupts = <2 4 0>;
		// interrupt-parent = <&mpc5200_pic>;
		//};

		ethernet@3000 {
		device_type = "network";
		compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
		reg = <0x3000 0x400>;
		local-mac-address = [ 00 00 00 00 00 00 ];
		interrupts = <2 5 0>;
		interrupt-parent = <&mpc5200_pic>;
		phy-handle = <&phy0>;
		};

		@@ -268,30 +233,24 @@
		compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
		reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
		interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
		interrupt-parent = <&mpc5200_pic>;

		phy0: ethernet-phy@0 {
		device_type = "ethernet-phy";
		reg = <0>;
		};
		};

		ata@3a00 {
		device_type = "ata";
		compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
		reg = <0x3a00 0x100>;
		interrupts = <2 7 0>;
		interrupt-parent = <&mpc5200_pic>;
		};

		i2c@3d00 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
		cell-index = <0>;
		reg = <0x3d00 0x40>;
		interrupts = <2 15 0>;
		interrupt-parent = <&mpc5200_pic>;
		fsl5200-clocking;
		};

		@@ -299,14 +258,13 @@
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
		cell-index = <1>;
		reg = <0x3d40 0x40>;
		interrupts = <2 16 0>;
		interrupt-parent = <&mpc5200_pic>;
		fsl5200-clocking;
		};

		sram@8000 {
		compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram","sram";
		compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
		reg = <0x8000 0x4000>;
		};
		};
		@@ -330,7 +288,6 @@
		0xc800 0 0 4 &mpc5200_pic 0 0 3>;
		clock-frequency = <0>; // From boot loader
		interrupts = <2 8 0 2 9 0 2 10 0>;
		interrupt-parent = <&mpc5200_pic>;
		bus-range = <0 0>;
		ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000
		0x02000000 0 0xa0000000 0xa0000000 0 0x10000000