Loading Documentation/devicetree/bindings/gpu/adreno.txt +8 −3 Original line number Diff line number Diff line Loading @@ -111,9 +111,6 @@ Optional Properties: Force the GPU to use 32 bit data sizes even if it is capable of doing 64 bit. - qcom,gpu-quirk-two-pass-use-wfi: Signal the GPU to set Set TWOPASSUSEWFI bit in A5XX_PC_DBG_ECO_CNTL (5XX only) - qcom,gpu-speed-bin: GPU speed bin information in the format <offset mask shift> offset - offset of the efuse register from the base. Loading @@ -130,6 +127,14 @@ Optional Properties: rendering thread is running on masked CPUs. Bit 0 is for CPU-0, bit 1 is for CPU-1... GPU Quirks: - qcom,gpu-quirk-two-pass-use-wfi: Signal the GPU to set Set TWOPASSUSEWFI bit in A5XX_PC_DBG_ECO_CNTL (5XX only) - qcom,gpu-quirk-critical-packets: Submit a set of critical PM4 packets when the GPU wakes up The following properties are optional as collecting data via coresight might not be supported for every chipset. The documentation for coresight properties can be found in: Loading arch/arm/boot/dts/qcom/msm8996-v3.dtsi +1 −0 Original line number Diff line number Diff line Loading @@ -103,6 +103,7 @@ /* Quirks */ qcom,gpu-quirk-two-pass-use-wfi; qcom,gpu-quirk-critical-packets; qcom,gpu-pwrlevel-bins { #address-cells = <1>; Loading arch/arm/boot/dts/qcom/msm8996pro.dtsi +2 −0 Original line number Diff line number Diff line Loading @@ -859,6 +859,8 @@ /* Updated chip ID */ qcom,chipid = <0x05030004>; /delete-property/ qcom,gpu-quirk-critical-packets; qcom,gpu-speed-bin = <0x413c 0x30000000 28>; qcom,gpu-pwrlevel-bins { Loading drivers/gpu/msm/adreno.c +5 −0 Original line number Diff line number Diff line Loading @@ -798,6 +798,7 @@ static struct { } adreno_quirks[] = { { ADRENO_QUIRK_TWO_PASS_USE_WFI, "qcom,gpu-quirk-two-pass-use-wfi" }, { ADRENO_QUIRK_IOMMU_SYNC, "qcom,gpu-quirk-iommu-sync" }, { ADRENO_QUIRK_CRITICAL_PACKETS, "qcom,gpu-quirk-critical-packets" }, }; static int adreno_of_get_power(struct adreno_device *adreno_dev, Loading Loading @@ -1004,6 +1005,7 @@ static void _adreno_free_memories(struct adreno_device *adreno_dev) static int adreno_remove(struct platform_device *pdev) { struct adreno_device *adreno_dev = adreno_get_dev(pdev); struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev); struct kgsl_device *device; if (adreno_dev == NULL) Loading @@ -1011,6 +1013,9 @@ static int adreno_remove(struct platform_device *pdev) device = KGSL_DEVICE(adreno_dev); if (gpudev->remove != NULL) gpudev->remove(adreno_dev); /* The memory is fading */ _adreno_free_memories(adreno_dev); Loading drivers/gpu/msm/adreno.h +3 −0 Original line number Diff line number Diff line Loading @@ -120,6 +120,8 @@ #define ADRENO_QUIRK_TWO_PASS_USE_WFI BIT(0) /* Lock/unlock mutex to sync with the IOMMU */ #define ADRENO_QUIRK_IOMMU_SYNC BIT(1) /* Submit critical packets at GPU wake up */ #define ADRENO_QUIRK_CRITICAL_PACKETS BIT(2) /* Flags to control command packet settings */ #define KGSL_CMD_FLAGS_NONE 0 Loading Loading @@ -696,6 +698,7 @@ struct adreno_gpudev { void (*snapshot)(struct adreno_device *, struct kgsl_snapshot *); void (*platform_setup)(struct adreno_device *); void (*init)(struct adreno_device *); void (*remove)(struct adreno_device *); int (*rb_init)(struct adreno_device *, struct adreno_ringbuffer *); int (*hw_init)(struct adreno_device *); int (*microcode_read)(struct adreno_device *); Loading Loading
Documentation/devicetree/bindings/gpu/adreno.txt +8 −3 Original line number Diff line number Diff line Loading @@ -111,9 +111,6 @@ Optional Properties: Force the GPU to use 32 bit data sizes even if it is capable of doing 64 bit. - qcom,gpu-quirk-two-pass-use-wfi: Signal the GPU to set Set TWOPASSUSEWFI bit in A5XX_PC_DBG_ECO_CNTL (5XX only) - qcom,gpu-speed-bin: GPU speed bin information in the format <offset mask shift> offset - offset of the efuse register from the base. Loading @@ -130,6 +127,14 @@ Optional Properties: rendering thread is running on masked CPUs. Bit 0 is for CPU-0, bit 1 is for CPU-1... GPU Quirks: - qcom,gpu-quirk-two-pass-use-wfi: Signal the GPU to set Set TWOPASSUSEWFI bit in A5XX_PC_DBG_ECO_CNTL (5XX only) - qcom,gpu-quirk-critical-packets: Submit a set of critical PM4 packets when the GPU wakes up The following properties are optional as collecting data via coresight might not be supported for every chipset. The documentation for coresight properties can be found in: Loading
arch/arm/boot/dts/qcom/msm8996-v3.dtsi +1 −0 Original line number Diff line number Diff line Loading @@ -103,6 +103,7 @@ /* Quirks */ qcom,gpu-quirk-two-pass-use-wfi; qcom,gpu-quirk-critical-packets; qcom,gpu-pwrlevel-bins { #address-cells = <1>; Loading
arch/arm/boot/dts/qcom/msm8996pro.dtsi +2 −0 Original line number Diff line number Diff line Loading @@ -859,6 +859,8 @@ /* Updated chip ID */ qcom,chipid = <0x05030004>; /delete-property/ qcom,gpu-quirk-critical-packets; qcom,gpu-speed-bin = <0x413c 0x30000000 28>; qcom,gpu-pwrlevel-bins { Loading
drivers/gpu/msm/adreno.c +5 −0 Original line number Diff line number Diff line Loading @@ -798,6 +798,7 @@ static struct { } adreno_quirks[] = { { ADRENO_QUIRK_TWO_PASS_USE_WFI, "qcom,gpu-quirk-two-pass-use-wfi" }, { ADRENO_QUIRK_IOMMU_SYNC, "qcom,gpu-quirk-iommu-sync" }, { ADRENO_QUIRK_CRITICAL_PACKETS, "qcom,gpu-quirk-critical-packets" }, }; static int adreno_of_get_power(struct adreno_device *adreno_dev, Loading Loading @@ -1004,6 +1005,7 @@ static void _adreno_free_memories(struct adreno_device *adreno_dev) static int adreno_remove(struct platform_device *pdev) { struct adreno_device *adreno_dev = adreno_get_dev(pdev); struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev); struct kgsl_device *device; if (adreno_dev == NULL) Loading @@ -1011,6 +1013,9 @@ static int adreno_remove(struct platform_device *pdev) device = KGSL_DEVICE(adreno_dev); if (gpudev->remove != NULL) gpudev->remove(adreno_dev); /* The memory is fading */ _adreno_free_memories(adreno_dev); Loading
drivers/gpu/msm/adreno.h +3 −0 Original line number Diff line number Diff line Loading @@ -120,6 +120,8 @@ #define ADRENO_QUIRK_TWO_PASS_USE_WFI BIT(0) /* Lock/unlock mutex to sync with the IOMMU */ #define ADRENO_QUIRK_IOMMU_SYNC BIT(1) /* Submit critical packets at GPU wake up */ #define ADRENO_QUIRK_CRITICAL_PACKETS BIT(2) /* Flags to control command packet settings */ #define KGSL_CMD_FLAGS_NONE 0 Loading Loading @@ -696,6 +698,7 @@ struct adreno_gpudev { void (*snapshot)(struct adreno_device *, struct kgsl_snapshot *); void (*platform_setup)(struct adreno_device *); void (*init)(struct adreno_device *); void (*remove)(struct adreno_device *); int (*rb_init)(struct adreno_device *, struct adreno_ringbuffer *); int (*hw_init)(struct adreno_device *); int (*microcode_read)(struct adreno_device *); Loading