Loading arch/arm/boot/dts/qcom/msm8996-pinctrl.dtsi +28 −0 Original line number Diff line number Diff line Loading @@ -464,6 +464,34 @@ }; }; i2c_8 { i2c_8_active: i2c_8_active { mux { pins = "gpio6", "gpio7"; function = "blsp_i2c8"; }; config { pins = "gpio6", "gpio7"; drive-strength = <4>; bias-disable; }; }; i2c_8_sleep: i2c_8_sleep { mux { pins = "gpio6", "gpio7"; function = "blsp_i2c8"; }; config { pins = "gpio6", "gpio7"; drive-strength = <4>; bias-pull-up; }; }; }; pmx_fm_int { fm_int_active: fm_int_active { mux { Loading arch/arm/boot/dts/qcom/msm8996.dtsi +23 −0 Original line number Diff line number Diff line Loading @@ -36,6 +36,7 @@ pci-domain1 = &pcie1; pci-domain2 = &pcie2; i2c7 = &i2c_7; i2c8 = &i2c_8; i2c12 = &i2c_12; spi0 = &spi_0; }; Loading Loading @@ -574,6 +575,28 @@ pinctrl-1 = <&i2c_7_sleep>; }; i2c_8: i2c@75b6000 { /* BLSP2 QUP2 */ compatible = "qcom,i2c-msm-v2"; #address-cells = <1>; #size-cells = <0>; reg-names = "qup_phys_addr"; reg = <0x75b6000 0x1000>; interrupt-names = "qup_irq"; interrupts = <0 102 0>; dmas = <&dma_blsp2 14 32 0x20000020 0x20>, <&dma_blsp2 15 32 0x20000020 0x20>; dma-names = "tx", "rx"; qcom,master-id = <84>; qcom,clk-freq-out = <400000>; qcom,clk-freq-in = <19200000>; clock-names = "iface_clk", "core_clk"; clocks = <&clock_gcc clk_gcc_blsp2_ahb_clk>, <&clock_gcc clk_gcc_blsp2_qup2_i2c_apps_clk>; pinctrl-names = "i2c_active", "i2c_sleep"; pinctrl-0 = <&i2c_8_active>; pinctrl-1 = <&i2c_8_sleep>; }; blsp1_uart2: uart@07570000 { /* BLSP1 UART2 */ compatible = "qcom,msm-hsuart-v14"; reg = <0x07570000 0x1000>, Loading Loading
arch/arm/boot/dts/qcom/msm8996-pinctrl.dtsi +28 −0 Original line number Diff line number Diff line Loading @@ -464,6 +464,34 @@ }; }; i2c_8 { i2c_8_active: i2c_8_active { mux { pins = "gpio6", "gpio7"; function = "blsp_i2c8"; }; config { pins = "gpio6", "gpio7"; drive-strength = <4>; bias-disable; }; }; i2c_8_sleep: i2c_8_sleep { mux { pins = "gpio6", "gpio7"; function = "blsp_i2c8"; }; config { pins = "gpio6", "gpio7"; drive-strength = <4>; bias-pull-up; }; }; }; pmx_fm_int { fm_int_active: fm_int_active { mux { Loading
arch/arm/boot/dts/qcom/msm8996.dtsi +23 −0 Original line number Diff line number Diff line Loading @@ -36,6 +36,7 @@ pci-domain1 = &pcie1; pci-domain2 = &pcie2; i2c7 = &i2c_7; i2c8 = &i2c_8; i2c12 = &i2c_12; spi0 = &spi_0; }; Loading Loading @@ -574,6 +575,28 @@ pinctrl-1 = <&i2c_7_sleep>; }; i2c_8: i2c@75b6000 { /* BLSP2 QUP2 */ compatible = "qcom,i2c-msm-v2"; #address-cells = <1>; #size-cells = <0>; reg-names = "qup_phys_addr"; reg = <0x75b6000 0x1000>; interrupt-names = "qup_irq"; interrupts = <0 102 0>; dmas = <&dma_blsp2 14 32 0x20000020 0x20>, <&dma_blsp2 15 32 0x20000020 0x20>; dma-names = "tx", "rx"; qcom,master-id = <84>; qcom,clk-freq-out = <400000>; qcom,clk-freq-in = <19200000>; clock-names = "iface_clk", "core_clk"; clocks = <&clock_gcc clk_gcc_blsp2_ahb_clk>, <&clock_gcc clk_gcc_blsp2_qup2_i2c_apps_clk>; pinctrl-names = "i2c_active", "i2c_sleep"; pinctrl-0 = <&i2c_8_active>; pinctrl-1 = <&i2c_8_sleep>; }; blsp1_uart2: uart@07570000 { /* BLSP1 UART2 */ compatible = "qcom,msm-hsuart-v14"; reg = <0x07570000 0x1000>, Loading